ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 77

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

PLA MMRS INTERFACE
The PLA peripheral interface consists of the 21 MMRs
described in the following sections.
PLAELMx Registers
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the look-up table, and bypass/use the flip-flop. See
Table 101 and Table 104.
Table 100. PLAELMx MMR Addresses (Default Value =
0x0000, Access is Read/Write)
Name
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
Table 102. Feedback Configuration
Bit
10:9
8:7
Value
00
01
10
11
00
01
10
11
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Address
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
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Table 101. PLAELMx MMR Bit Descriptions
Bit
31:11
10:9
8:7
6
5
4:1
0
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Reserved.
Mux 0 control (see Table 104).
Mux 1 control (see Table 104).
Mux 2 control.
Set by the user to select the output of Mux 0.
Cleared by the user to select the bit value from
PLADIN.
Mux 3 control.
Set by the user to select the input pin of the
particular element.
Cleared by the user to select the output of Mux 1.
Look up table control.
0.
NOR.
B AND NOT A.
NOT A.
A AND NOT B.
NOT B.
EXOR.
NAND.
AND.
EXNOR.
B.
NOT A OR B.
A.
A OR NOT B.
OR.
1.
Mux 4 control.
Set by the user to bypass the flip-flop.
Cleared by the user to select the flip-flop
(cleared by default).
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
ADuC7121