ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 80

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
INTERRUPT SYSTEM
Table 108. IRQ/FIQ MMRs Bit Designations
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
There are 27 interrupt sources on the ADuC7121 that are con-
trolled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core recognizes interrupts as one of two types only: a
normal interrupt request (IRQ) and a fast interrupt request
(FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is managed
through a number of interrupt related registers. The bits in each
IRQ and FIQ register represent the same interrupt source as
described in Table 108.
The ADuC7121 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full-vectored interrupt controller is
enabled.
Description
All interrupts OR’ed (FIQ only)
Software interrupt
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
IDAC fault
PSM
Undefined
Flash Control 0
Flash Control 1
ADC
UART
SPI
I
I
I
I
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
XIRQ2 (GPIO IRQ2 )
XIRQ3 (GPIO IRQ3)
PWM
XIRQ4 (GPIO IRQ4 )
XIRQ5 (GPIO IRQ5)
PLA IRQ0
PLA IRQ1
2
2
2
2
C0 Master IRQ
C0 Slave IRQ
C1 Master IRQ
C1 Slave IRQ
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Comments
This bit is set if any FIQ is active
User programmable interrupt source
General-Purpose Timer0
General-Purpose Timer1
General-Purpose Timer2 or wake-up timer
General-Purpose Timer3 or watchdog timer
General-Purpose Timer4
IDAC fault IRQ
Power supply monitor
This bit is not used
Flash controller for Block 0 interrupt
Flash controller for Block 1 interrupt
ADC interrupt source bit
UART interrupt source bit
SPI interrupt source bit
I
I
I
I
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
PWM trip interrupt source bit
External Interrupt 4
External Interrupt 5
PLA Block 0 IRQ bit
PLA Block 1 IRQ bit
2
2
2
2
C master interrupt source bit
C slave interrupt source bit
C master interrupt source bit
C slave interrupt source bit
Upon entering the interrupt service routine (ISR), immediately
save IRQSTA/FIQSTA to ensure that all valid interrupt sources
are serviced.
NORMAL INTERRUPT REQUEST (IRQ)
The normal interrupt request (IRQ) is the exception signal
to enter the IRQ mode of the processor. It services general-
purpose interrupt handling of internal and external events.
All 32 bits are logically OR’ e d to create a single IRQ signal to the
ARM7TDMI core. The four 32-bit registers dedicated to IRQ
follow.
IRQSIG Register
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is a
read-only register. Do not use this register in an interrupt service
routine for determining the source of an IRQ exception; use
only IRQSTA for this purpose.