AD7711 Analog Devices, AD7711 Datasheet - Page 6

• Manufacturer Part Number: AD7711
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Excitation Currents
• Manufacturer: Analog Devices

Specifications of AD7711

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Parameter
External Clocking Mode
NOTES
8
Specifications subject to change without notice.
AD7711
TIMING CHARACTERISTICS
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
f
SCLK
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
7
7
8
8
TO OUTPUT
PIN
100pF
Limit at T
(A, S Versions)
f
0
0
2 ¥ t
0
4 ¥ t
10
2 ¥ t
2 ¥ t
2 ¥ t
t
10
t
10
5 ¥ t
0
0
4 ¥ t
2 ¥ t
30
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
1.6mA
200 A
/5
+ 10
+ 10
/2 + 50
MIN
+ 20
– SCLK High
, T
+2.1V
MAX
Unit
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
–6–
Conditions/Comments
Serial Clock Input Frequency
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to DRDY High
SCLK to Data Valid Hold Time
RFS/TFS to SCLK Falling Edge Hold Time
RFS to Data Valid Hold Time
A0 to TFS Setup Time
A0 to TFS Hold Time
SCLK Falling Edge to TFS Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
MCLK OUT
MCLK IN
AIN1(+)
AIN1(–)
MODE
PIN CONFIGURATION
SYNC
SCLK
RTD1
RTD2
AV
V
A0
DD
SS
DIP AND SOIC
10
11
12
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD7711
24
23
22
21
20
19
18
17
16
15
14
13
DGND
DV
DRDY
RFS
TFS
AGND
AIN2
REF OUT
REF IN(+)
REF IN(–)
V
SDATA
BIAS
DD
REV. G