AD7711 Analog Devices, AD7711 Datasheet - Page 23

• Manufacturer Part Number: AD7711
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Excitation Currents
• Manufacturer: Analog Devices

Specifications of AD7711

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line and does not have any effect on the status of
DRDY. A write operation to the control register or the calibra-
tion register must always write 24 bits.
Figure 13a shows a write operation to the AD7711 with TFS
remaining low for the duration of the operation. A0 determines
whether a write operation transfers data to the control register
or to the calibration registers. This A0 signal must remain valid
for the duration of the serial write operation. As before, the serial
clock line should be low between read and write operations. The
serial data to be loaded to the AD7711 must be valid on the
high level of the externally applied SCLK signal. Data is clocked
into the AD7711 on the high level of this SCLK signal with the
REV.G
SDATA (I)
SDATA (I)
( TFS Returns High during Write Operation)
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation
SCLK (I)
SCLK (I)
TFS (I)
TFS (I)
A0 (I)
A0 (I)
t
32
t
32
MSB
t
35
MSB
t
26
t
35
t
–23–
36
t
26
t
27
MSB transferred first. On the last active high time of SCLK, the
LSB is loaded to the AD7711.
Figure 13b shows a timing diagram for a write operation to the
AD7711 with TFS returning high during the operation and
returning low again to write the rest of the data-word. Timing
parameters and functions are very similar to that outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when TFS returns high in the middle
of transferring a word.
Data to be loaded to the AD7711 must be valid prior to the
rising edge of the SCLK signal. TFS should return high during
the low time of SCLK. After TFS returns low again, the next bit
of the data-word to be loaded to the AD7711 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7711.
t
t
27
BIT N
36
t
30
t
35
BIT N+1
LSB
t
34
t
36
t
33
AD7711
2