AD7711 Analog Devices, AD7711 Datasheet - Page 19

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AD7711

Manufacturer Part Number
AD7711
Description
CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Excitation Currents
Manufacturer
Analog Devices
Datasheet

Specifications of AD7711

Resolution (bits)
24bit
# Chan
2
Sample Rate
19.5kSPS
Interface
Ser
Analog Input Type
Diff-Bip,Diff-Uni,SE-Uni
Ain Range
Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
Adc Architecture
Sigma-Delta
Pkg Type
DIP,SOIC

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Measurement errors due to offset drift or gain drift can be elimi-
nated at any time by recalibrating the converter or by operating
the part in the background calibration mode. Using the system
calibration mode can also minimize offset and gain errors in the
signal conditioning circuitry. Integral and differential linearity
errors are not significantly affected by temperature changes.
POWER SUPPLIES AND GROUNDING
Because the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. V
currents flowing in the analog modulator. As a result, the V
input should be driven from a low impedance to minimize errors
due to charging/discharging impedances on this line. When the
internal reference is used as the reference source for the part,
AGND is the ground return for this reference voltage.
The analog and digital supplies to the AD7711 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The digital filter will
provide rejection of broadband noise on the power supplies,
except at integer multiples of the modulator sampling frequency.
The digital supply (DV
supply (AV
analog and digital supplies are used, the recommended decoupling
scheme is shown in Figure 9. In systems where AV
DV
driven from the same 5 V supply, although each supply should be
decoupled separately as shown in Figure 9. It is preferable that
the common supply is the system’s analog 5 V supply.
REV.G
DD
= 5 V, it is recommended that AV
BIAS
DD
) by more than 0.3 V in normal operation. If separate
provides the return path for most of the analog
DD
) must not exceed the analog positive
DD
and DV
DD
= 5 V and
DD
are
BIAS
–19–
It is also important that power is applied to the AD7711 before
signals at REF IN, AIN, or the logic input pins in order to avoid
latch-up. If separate supplies are used for the AD7711 and the
system digital circuitry, the AD7711 should be powered up first.
If it is not possible to guarantee this, current limiting resistors
should be placed in series with the logic inputs.
DIGITAL INTERFACE
The AD7711’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers, and digital signal processors.
A serial read to the AD7711 can access data from the output
register, the control register, or the calibration registers. A serial
write to the AD7711 can write data to the control register or the
calibration registers.
Two different modes of operation are available, optimized for
different types of interfaces where the AD7711 can act either as
master in the system (it provides the serial clock) or as slave (an
external serial clock can be provided to the AD7711). These
two modes, labelled self-clocking mode and external clocking
mode, are discussed in detail in the following sections.
Figure 9. Recommended Decoupling Scheme
ANALOG
SUPPLY
10 F
0.1 F
AD7711
AV
DD
DV
DD
0.1 F
DIGITAL 5V
SUPPLY
AD7711
2

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