AD7711 Analog Devices, AD7711 Datasheet
AD7711
Specifications of AD7711
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AD7711 Summary of contents
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... RTD current control, and calibration modes. 4. The AD7711 allows the user to read and to write the on-chip calibration registers. This means that the microcontroller has much greater control over the calibration procedure. ...
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... AD7711–SPECIFICATIONS +2.5 V; REF IN(–) = AGND; MCLK MHz unless otherwise stated. All specifications T Parameter STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity @ 25∞ MIN MAX 2, 3 Positive Full-Scale Error 5 Full-Scale Drift 2 Unipolar Offset Error 5 Unipolar Offset Drift 2 Bipolar Zero Error ...
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... Output Compliance SYSTEM CALIBRATION 14 Positive Full-Scale Calibration Limit 14 Negative Full-Scale Calibration Limit 15 Offset Calibration Limit 15 Input Span NOTES 12 The AD7711 is tested with the following V BIAS with and V = – BIAS 13 Guaranteed by design, not production tested. 14 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s. ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7711 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... The AD7711 is specified with a 10 MHz clock for AV than 10 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5 ...
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... PIN CONFIGURATION DIP AND SOIC SCLK 1 24 DGND MCLK MCLK OUT SDATA 3 22 DRDY RFS SYNC 5 20 AD7711 TFS MODE 6 19 TOP VIEW (Not to Scale) AIN1(+) 7 18 AGND AIN1(– AIN2 RTD1 REF OUT 9 16 RTD2 REF IN(+) 10 15 ...
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... Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. During a write operation to the AD7711, the SDATA line should not return to high impedance until after TFS returns high. ...
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... AD7711 can accept and still calibrate offset accurately. Full-Scale Calibration Range This is the range of voltages that the AD7711 can accept in the system calibration mode and still calibrate full-scale correctly. Input Span In system calibration schemes, two voltages applied in sequence to the AD7711’ ...
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... Activate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, the AD7711 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. The major advantage is that the user does not have to recalibrate the device when there is a change in the ambient temperature ...
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... FS11 and is in the range 19 to 2,000. With the nominal MHz, this results in a first notch frequency range from 9. 1.028 kHz. To ensure correct operation of the AD7711, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. ...
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... Effective Resolution * (Bits) Gain of 2 Gain of 4 Gain of 8 21 19.5 18.5 18.5 18.5 15 15 –11– AD7711 /GAIN, or the input full scale pos- REF Gain of 16 Gain of 32 Gain of 64 0.25 0.25 0.25 0.44 0.41 0.38 0.46 0.43 0.4 0.54 0.46 0.46 0.63 0.62 0.6 1.1 0.9 0.65 7 180 120 70 Gain of 16 Gain of 32 Gain of 64 Gain of 128 20 ...
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... The AD7711 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the device calibra- tion coefficients and also to write its own calibration coefficients to the part from prestored values in E – ...
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... ADCs. Using the quantization noise formula for an ADC, SNR = (6.02 ¥ number of bits + 1.76) dB, a 1-bit ADC or comparator yields an SNR of 7.78 dB. The AD7711 samples the input signal at a frequency of 39 kHz or greater (see Table III result, the quantization noise is spread over a much wider frequency than that of the band of interest ...
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... AD7711. For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7711 at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz. Post filtering can be applied to this to reduce the bandwidth and output noise to the 7 ...
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... In this case 12.5 kW resistor is used, the 200 mA current source generates 2.5 V across the resistor. This 2.5 V can be applied to the REF IN(+) input of the AD7711 and with the REF IN(–) input at ground, it will supply 2.5 V for the part. For 3-wire RTD configura- ...
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... REF OUT to REF IN) results in degraded output noise perfor- mance from the AD7711 for portions of the noise table that are dominated by the device noise. The on-chip reference noise effect is eliminated in ratiometric applications where the refer- ence is used to provide the excitation voltage for the analog front end ...
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... AD7711 are acceptable, and no calibra- tion is performed after power-on, issuing a SYNC pulse to the AD7711 resets the AD7711’s digital filter logic the SYNC line, with R, C time constant longer than the DV power-on time, performs the SYNC function. ...
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... MD2, MD1, MD0 of the control register. When invoked, the background calibration mode reduces the output data rate of the AD7711 by a factor of 6 while the –3 dB bandwidth remains unchanged. The advantage is that the part is continually per- forming calibration and automatically updating its calibration coefficients ...
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... A serial read to the AD7711 can access data from the output register, the control register, or the calibration registers. A serial write to the AD7711 can write data to the control register or the calibration registers and DD ...
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... SCLK output. With DRDY low, the RFS input is brought low. RFS going low enables the serial clock of the AD7711 and also places the MSB of the word on the serial data line. All subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the follow- ing rising edge of this clock ...
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... Figure 11 assumes a pull-up resistor on the SCLK line.) External Clocking Mode The AD7711 is configured for external clocking mode by tying the MODE pin low. In this mode, SCLK of the AD7711 is config- ured as an input, and an external serial clock must be provided to this SCLK pin. This external clocking mode is designed for direct ...
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... Figures 12a and 12b show timing diagrams for reading from the AD7711 in external clocking mode. In Figure 12a, all the data is read from the AD7711 in one operation. In Figure 12b, the data is read from the AD7711 over a number of read operations. Both read operations show a read from the AD7711’s output data register ...
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... TFS returns high in the middle of transferring a word. Data to be loaded to the AD7711 must be valid prior to the rising edge of the SCLK signal. TFS should return high during the low time of SCLK. After TFS returns low again, the next bit of the data-word to be loaded to the AD7711 is clocked in on next high level of the SCLK input ...
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... MSB or the LSB. The AD7711 expects the MSB as the first bit in the data stream. In cases where the data is being read or being written in bytes and the data has to be reversed, the bits have to be reversed for every byte. – ...
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... The AD7711 is configured for external clocking mode, while the 8XC51 is configured in its Mode 0 serial interface mode. The DRDY line from the AD7711 is connected to the Port P1.2 input of the 8XC51, so the DRDY line is polled by the 8XC51. The DRDY line can be connected to the INT1 input of the 8XC51 if an interrupt driven system is preferred ...
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... SPI port is used on the 68HC11 is in single-chip mode. The DRDY line from the AD7711 is connected to the Port PC2 input of the 68HC11, so the DRDY line is polled by the 68HC11. The DRDY line can be connected to the IRQ input of the 68HC11 if an interrupt driven system is preferred ...
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... AIN1(+) and AIN1(–). Twice the voltage is developed across R but because this is a common-mode L3 voltage, it will not introduce any errors. The circuit in Figure 20 shows the reference voltage for the AD7711 derived from the part’s own internal reference. ANALOG 5V SUPPLY AV DV ...
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... Revision History Location 3/04—Data Sheet changed from REV REV. G. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Deleted AD7711 to ADSP-2105 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Changes to AD7711 to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTLINE DIMENSIONS 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) ...