AD7711 Analog Devices, AD7711 Datasheet - Page 27

• Manufacturer Part Number: AD7711
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Excitation Currents
• Manufacturer: Analog Devices

Specifications of AD7711

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

3-Wire RTD Configurations
One possible 3-wire configuration using the AD7711 is outlined
in Figure 20. In the 3-wire configuration, the lead resistances
will result in errors if only one current source is used because
the 200 mA will flow through R
between AIN1(+) and AIN1(–). In the scheme outlined below,
the second RTD current source is used to compensate for the
error introduced by the 200 mA flowing through R
RTD current flows through R
equal (the leads would normally be of the same material and of
equal length) and RTD1 and RTD2 match, then the error voltage
across R
is developed between AIN1(+) and AIN1(–). Twice the voltage
is developed across R
voltage, it will not introduce any errors. The circuit in Figure 20
shows the reference voltage for the AD7711 derived from the
part’s own internal reference.
REV.G
Figure 20. 3-Wire RTD Application with the AD7711
L2
equals the error voltage across R
REF IN(–)
RTD
R
R
R
L2
L3
L1
RTD1
RTD2
ANALOG 5V SUPPLY
L3
AIN1(+)
AIN1(–)
AGND
but because this is a common-mode
AV
200 A
200 A
DD
DGND
L2
PGA
L1
DV
. Assuming R
, developing a voltage error
A = 1–128
DD
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
AD7711
V
SS
(4.57)
REF IN(+)
0.180
MAX
CIRCUITRY
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
L1
INTERNAL
24-Lead Plastic Dual In-Line Package [PDIP]
REFERENCE
and no error voltage
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
L1
2.5V
Dimensions shown in inches and (millimeters)
L1
24
1
and R
REF OUT
. The second
COMPLIANT TO JEDEC STANDARDS MO-095AG
OUTLINE DIMENSIONS
1.185 (30.01)
1.165 (29.59)
1.145 (29.08)
L2
(2.54)
0.100
BSC
are
0.015 (0.38) MIN
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
(N-24)
–27–
12
13
The circuit in Figure 21 shows an alternate 3-wire configura-
tion. In this case, the circuit has the same benefits in terms of
eliminating lead resistance errors as outlined in Figure 20, but it
has the additional benefit that the reference voltage is derived
from one of the current sources. This gives all the benefits of
eliminating RTD tempco errors as outlined in Figure 19. The
voltage on either RTD input can go to within 2 V of the AV
supply. The circuit is shown for a 2.5 V reference.
SEATING
PLANE
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
12.5k
RTD
R
R
Figure 21. Alternate 3-Wire Configuration
R
L2
L3
L1
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
RTD1
RTD2
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
AGND
AIN1(+)
AIN1(–)
AV
DD
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
200 A
200 A
DV
DGND
DD
PGA
REF IN(–)
AD7711
V
A = 1–128
SS
REF IN(+)
CIRCUITRY
INTERNAL
AD7711
DD
2