AD9866 Analog Devices, AD9866 Datasheet - Page 41

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Because the CPGA processes signals in the continuous time
domain, its performance vs. bias setting remains mostly
independent of the sample rate. Table 25 shows how the typical
current consumption seen at AVDD (Pins 35 and 40) varies as a
function of Bits (7:5), while the remaining bits are maintained at
their default settings of 0. Only four of the possible settings
result in any reduction in current consumption relative to the
default setting. Reducing the bias level typically results in a
degradation in the THD vs. frequency performance as shown in
Figure 80. This is due to a reduction of the amplifier’s unity gain
bandwidth, while the SNR performance remains relatively
unaffected.
Table 25. Analog Supply Current vs. CPGA Bias Settings at
f
Bit 7
0
0
0
0
1
1
1
1
ADC
= 65 MSPS
65.0
62.5
60.0
57.5
55.0
52.5
50.0
47.5
45.0
42.5
40.0
(000,001,010,100 with RxPGA = 0 and +36 dB and AIN = −1 dBFS,
000
Figure 80. THD vs. f
LPF set to 26 MHz and f
Bit 6
0
0
1
1
0
0
1
1
001
CPGA BIAS SETTING-BITS (7:5)
IN
Performance and RxPGA Bias Settings
SNR_RxPGA = 0dB
SNR_RxPGA = 36dB
THD_RxPGA = 0dB
THD_RxPGA = 36dB
010
Bit 5
0
1
0
1
0
1
0
1
ADC
= 50 MSPS)
011
∆ mA
0
−27
−42
−51
−55
27
69
27
100
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
Rev. B | Page 41 of 48
The SPGA is implemented as a switched capacitor amplifier;
therefore, its performance vs. bias level is mostly dependent on
the sample rate. Figure 81 shows how the typical current
consumption seen at AVDD (Pin 35 and Pin 40) varies as a
function of Bits (4:3) and sample rate, while the remaining bits
are maintained at the default setting of 0. Figure 82 shows how
the SNR and THD performance is affected for a 10 MHz sine
wave input as the ADC sample rate is swept from 20 MHz to
80 MHz.
Figure 82. SNR and THD Performance vs. f
Figure 81. AVDD Current vs. SPGA Bias Setting and Sample Rate
65
64
63
62
61
60
59
58
57
56
55
210
205
200
195
190
185
180
175
170
20
20
RxPGA = 0 dB, f
30
30
ADC SAMPLE RATE (MSPS)
40
SAMPLE RATE (MSPS)
40
IN
= 10 MHz. AIN = −1 dBFS
01
00
10
11
50
THD-00
THD-01
THD-10
THD-11
50
ADC
60
and SPGA Bias Setting with
60
SNR-00
SNR-01
SNR-10
SNR-11
70
70
AD9866
80
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
80