AD9866 Analog Devices, AD9866 Datasheet - Page 26

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9866
RxPGA CONTROL
The AD9866 contains a digital PGA in the Rx path that is used
to extend the dynamic range. The RxPGA can be programmed
over a −12 dB to +48 dB with 1 dB resolution using a 6-bit word,
and with a 0 dB setting corresponding to a 2 V p-p input signal.
The 6-bit word is fed into a LUT that is used to distribute the
desired gain over three amplification stages within the Rx path.
Upon power-up, the RxPGA gain register is set to its minimum
gain of −12 dB. The RxPGA gain mapping is shown in Figure 56.
Table 15 lists the SPI registers pertaining to the RxPGA.
Table 15. SPI Registers RxPGA Control
Address
(Hex)
0x09
0x0B
The RxPGA gain register can be updated via the Tx[5:0] port,
the PGA[5:0] port, or the SPI port. The first two methods allow
fast updates of the RxPGA gain register and should be consid-
ered for digital AGC functions requiring a fast closed-loop
response. The SPI port allows direct update and readback of the
RxPGA gain register via Register 0x09 with an update rate
limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 of
Register 0x09 must be set for a read or write operation.
Updating the RxPGA via the Tx[5:0] port is an option only in
full-duplex mode.
with TXSYNC low, programs the PGA setting on either the
rising edge or falling edge of RXCLK, as shown in Figure 57.
The GAIN pin must be held high, TXSYNC must be held low,
and GAIN data must be stable for one or more clock cycles to
update the RxPGA gain setting. A low level on the GAIN pin
enables data to be fed to the digital interpolation filter. This
–12
48
42
36
30
24
18
12
–6
6
0
0
Bit
(6)
(5:0)
(6)
(5)
(3)
(2)
(1)
6
Figure 56. Digital Gain Mapping of RxPGA
6-BIT DIGITAL WORD-DECIMAL EQUIVALENT
12
1
In this case, a high level on the GAIN pin
Description
Enable RxPGA update via SPI
RxPGA gain code
Select TxPGA via PGA[5:0]
Select RxPGA via PGA[5:0]
Enable software GAIN strobe – full-duplex
Enable RxPGA update via Tx[5:0] – full-duplex
3-bit RxPGA gain mapping – half-duplex
18
24
30
36
42
48
54
60
66
Rev. B | Page 26 of 48
2
interface should be considered when upgrading existing designs
from the AD9876 MxFE product or half-duplex applications
trying to minimize an ASIC’s pin count.
Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an
option for both the half-duplex
PGA port consists of an input buffer that passes the 6-bit data
appearing at its input directly to the RxPGA (or TxPGA) gain
register with no gating signal required. Bit 5 or Bit 6 of
Register 0x0B is used to select whether the data updates the
RxPGA or TxPGA gain register. In applications that switch
between RxPGA and TxPGA gain control via PGA[5:0], be
careful that the RxPGA (or TxPGA) is not inadvertently loaded
with the wrong data during a transition. In the case of an
RxPGA to TxPGA transition, first deselect the RxPGA gain
register, update the PGA[5:0] port with the desired TxPGA gain
setting, and then select the TxPGA gain register.
The RxPGA also offers an alternative 3-bit word gain mapping
option
as shown in Table 16. The 3-bit word is directed to PGA[5:3] with
PGA[5] being the MSB. This feature is backward-compatible with
the AD9975 MxFE, and allows direct interfacing to the CX11647 or
INT5130 HomePlug 1.0 PHYs.
Table 16. PGA Timing for AD9975 Backward-Compatible
Mode
PGA[5:3]
000
001
010
011
100
101
110
111
1
2
3
4
Default setting for full-duplex mode (MODE = 1).
The GAIN strobe can also be set in software via Register 0x0B, Bit 3 for
continuous updating. This eliminates the requirement for external GAIN
signal, reducing the ASIC pin count by 1.
Default setting for half-duplex mode (MODE = 0).
Default setting for MODE = 0 and CONFIG =1.
Tx
Tx
RXCLK
SYNC
GAIN
[5:0]
4
Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode
that provides a −12 dB to +36 dB span in 8 dB increments
Digital Gain Setting
Decimal
0
1
2
3
4
5
6
7
t
SU
3
and full-duplex interfaces. The
GAIN
Gain (dB)
−12
−12
−4
4
12
20
28
36
t
HD