AD9866 Analog Devices, AD9866 Datasheet
AD9866
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AD9866 Summary of contents
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... APPLICATIONS Powerline networking VDSL and HPNA GENERAL DESCRIPTION The AD9866 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well-suited for half- and full-duplex applications. The digital interface is ...
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... AD9866 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications........................................................ 5 Digital Specifications ................................................................... 6 Serial Port Timing Specifications ............................................... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ................................................................................ 7 Full-Duplex Data Interface (Tx and Rx PORT) Timing Specifications ...
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... Monotonic ±2 0.5 66.6 69.2 68.4 69.8 −79 −68.7 68 105 2 150 43.3 45.2 −19.5 0 0.5 Monotonic 0.5 1.23 0.7 3 0.2187 0.2405 50 96 0.1095 0.1202 50 AD9866 Unit Bits MSPS μ dBm dBc dBc dBc dBc dBm dBc ppm/ C Cycles f /f OUT DAC f /f OUT ...
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... AD9866 Parameter PLL CLK MULTIPLIER OSCIN Frequency Range Internal VCO Frequency Range Duty Cycle OSCIN Impedance 5 CLKOUT1 Jitter 6 CLKOUT2 Jitter 7 CLKOUT1 and CLKOUT2 Duty Cycle 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and p-p differential analog input). ...
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... DATA Test Level Min Typ Max V 3.135 3.3 3.465 V 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 3.3 3.6 II 406 475 IV 311 342 IV 95 133 AD9866 Unit Cycles Cycles dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Unit ...
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... AD9866 Parameter POWER CONSUMPTION (Half-Duplex Operation with f Tx Mode AVDD CLKVDD DVDD DRVDD Rx Mode AVDD CLKVDD DVDD DRVDD POWER CONSUMPTION OF FUNCTIONAL BLOCKS RxPGA and LPF ADC TxDAC IAMP (Programmable) Reference CLK PLL and Synthesizer MAXIMUM ALLOWABLE POWER DISSIPATION ...
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... Full IV DV Full IV Temp Test Level Full II Full II Full II Full II Full II Full II Full II Full II Full II Full II Full II Full II Rev Page AD9866 Min Typ Max Unit 32 MHz MHz Min ...
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... AD9866 FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. Parameter Tx PATH INTERFACE (See Figure 53) Input Nibble Rate (2× Interpolation) Input Nibble Rate (4× Interpolation) Tx Data Setup Time ( Data Hold Time ( ...
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... V to DRVDD + 0.3 V testing maximum V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design −40°C to +85°C and characterization for industrial temperature range. 125°C ESD CAUTION −65°C to +150°C Rev Page AD9866 ...
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... ADIO1 Rx[1] 12 ADIO0 Rx[0] 13 RXEN RXSYNC 14 TXEN TXSYNC PIN 1 3 IDENTIFIER AD9866 7 TOP VIEW 8 (Not to Scale Figure 2. Pin Configuration 1 Mode Description HD MSB of ADIO Buffer FD MSB of Tx Nibble Input ...
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... Power-Up SPI Register Default Setting Input Clock Oscillator/Synthesizer Supply Return Crystal Oscillator Inverter Output Crystal Oscillator Inverter Input Clock Oscillator/Synthesizer Supply Digital Supply Return Digital Supply Input f /L Clock Output OSCIN Power-Down Input The exposed pad must be soldered to GND. Rev Page AD9866 ADC ...
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... AD9866 TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 FUND = –1dBFS SINAD = 61.9dBFS 0 ENOB = 10BITS SNR = 64.5dBFS –10 THD = –65.4dBFS SFDR = –64.9dBc (THIRD HARMONIC) –20 RBW = 12.21kHz – ...
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... Figure 13. THD vs. RxPGA Gain and Frequency 65 SINAD @ +25°C SINAD @ +85°C 61 SINAD @ –40° THD @ +25°C 44 THD @ +85°C THD @ –40°C 41 – RxPGA GAIN (dB MHz) IN AD9866 10.5 5MHz 10.0 10MHz 15MHz 20MHz 9.5 30MHz 9.0 8.5 8.0 7.5 7.0 6 5MHz 10MHz 15MHz 20MHz 30MHz –40 –45 –50 – ...
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... MHz; AIN = −1 dB; RxPGA = 48 dB) (50 MSPS 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 AD9866: GAIN STEP ERROR @ +25°C –0.4 AD9866: GAIN STEP ERROR @ +85°C AD9866: GAIN STEP ERROR @ –40°C –0.5 – RxPGA GAIN (dB) Figure 20. RxPGA Gain Step Error vs. Gain (f –20 –25 –30 –35 – ...
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... INPUT FREQUENCY (MHz) (LPF MHz) − FREQUENCY (MHz) Figure 26. Rx Input Impedance vs. Frequency AD9866 560 640 720 –6dB GAIN 0dB GAIN +6dB GAIN ...
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... AD9866 TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS and 80 MSPS, RSET = 1.96 kΩ, 2:1 transformer coupled output (see Figure 63) into 50 Ω load half-or full-duplex interface, default power bias settings –10 –20 –30 –40 –50 –60 –70 – ...
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... FREQUENCY (MHz MSPS, 2× Interpolation) DATA 2-TONE IMD SNR –24 –21 –18 –15 –12 –9 –6 AOUT (dBFS) Figure 38. SNR and SFDR vs. P OUT ( MHz MSPS, 2× Interpolation) OUT DATA AD9866 35 40 140 160 –3 0 ...
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... AD9866 IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3 Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 – FREQUENCY (MHz) Figure 39. Dual-Tone Spectral Plot of IAMPN Output (IAMP Settings 12.5 mA 2:1 Transformer into 75 Ω ...
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... Rev Page AD9866 Comments CONFIG = 1 0 Default SPI configuration is 3-wire, MSB first PWR_DWN = 0. Default setting is for all 0 blocks powered on PWR_DWN = 1. Default setting* is for all 1 ...
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... AD9866 Bit Address Break- 1 (Hex) down Description Rx PATH CONTROL 0x07 (5) Initiate Offset Cal. (4) Rx Low Power (0) Rx Filter ON 0x08 (7:0) Rx Filter Tuning Cutoff Frequency Tx/Rx PATH GAIN CONTROL 0x09 (6) Use SPI Rx Gain (5:0) Rx Gain Code 0x0A (6) Use SPI Tx Gain (5:0) Tx Gain Code Tx AND Rx PGA CONTROL ...
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... Tx path and RxPGA gain mapping. SERIAL PORT INTERFACE (SPI) The serial port of the AD9866 has 3- or 4-wire SPI capability allowing read/write access to all registers that configure the device’s internal parameters. Registers pertaining to the SPI are listed in Table 11 ...
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... LSB first. Multibyte data trans- fers in LSB format can be completed by writing an instruction byte that includes the register address of the first address to be accessed. The AD9866 automatically increments the address for each successive byte required for the multibyte communication cycle. ...
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... The phase relationships among the TXCLK, RXCLK, and OSCIN signals can be arbitrary. If the digital ASIC cannot provide a low jitter clock source to OSCIN, use the AD9866 to generate the clock for its DAC and ADC, and pass the desired clock signal to the digital ASIC via CLKOUT1 or CLKOUT2. ...
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... Rx ADC tional block remains powered on. A buffered version of the signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05. This feature allows the AD9866 to be completely powered down (including the clock synthesizer) while serving as the master. The Tx[5:0] port operates in the following manner with the SPI register default settings ...
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... Figure 55 shows a possible digital interface between an ASIC DH and the AD9866. The AD9866 serves as the master generating the required clocks for the ASIC. This interface requires that the ASIC reserve 16 pins for the interface, assuming a 6-bit nibble width and the use of the Tx port for RxPGA gain control ...
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... AD9866 RxPGA CONTROL The AD9866 contains a digital PGA in the Rx path that is used to extend the dynamic range. The RxPGA can be programmed over a − +48 dB with 1 dB resolution using a 6-bit word, and with setting corresponding p-p input signal. The 6-bit word is fed into a LUT that is used to distribute the desired gain over three amplification stages within the Rx path ...
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... TXPGA CONTROL The AD9866 also contains a digital PGA in the Tx path distributed between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A 6-bit word is used to set the TxPGA attenuation according to the mapping shown in Figure 58 ...
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... TxDAC, and a current-output amplifier (IAMP), as shown in Figure 59. Note that the additional two bits of resolution offered by the AD9866 (vs. the AD9865) result reduction in the pass-band noise floor. The digital interpolation filter relaxes the Tx analog filtering requirements by simultaneously reducing the images from the DAC reconstruction process while increasing the analog filter’ ...
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... Programmable current sources I can be used to improve the primary and secondary path mirrors’ linearity performance under certain conditions by increasing their signal-to-standing current ratio. This feature provides a Rev Page AD9866 value at the REFADJ SET ) SET value of 1.96 kΩ results in I equal to ...
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... AD9866 marginal improvement in distortion performance under large signal conditions when the peak ac current of the reconstructed waveform frequently approaches the dc standing current within the TxDAC (0 to −1 dBFS sine wave) causing the internal mirrors to turn off. However, the improvement in distortion performance diminishes as the crest factor (peak-to-rms ratio) of the ac signal increases. Most applications can disable these current sources (set via Register 0x12) to reduce the IAMP’ ...
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... R × (N × while the common-mode PK drop below this level (AVDD − VOUT × I {(AVDD − VOUT ) × N IAMP PK − 0.65) × via a 0.1 μF blocking capacitor and series resistor of 1 Ω AD9866 R 0.1μ LOAD R 0.1μF S (4) − 0.65 (5) ...
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... This feature is advantageous in half-duplex applications (for example, power lines) in which the Tx output driver must go into a high impedance state while in Rx mode. If the AD9866 is configured for the half-duplex mode (MODE = 0), the IAMP, TxDAC, and interpolation filter are automatically powered ...
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... RxPGA, a 3-pole programmable LPF, and a 12-bit (or 10-bit) ADC. Note that the additional 2 bits of resolution offered by the AD9866 (vs. the AD9865) result lower noise floor depending on the RxPGA gain setting and LPF cutoff frequency. Also working in conjunction with the receive path is an offset correction circuit ...
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... AD9866 calibration routine lasting less than 100 μs automatically occurs each time the target cutoff frequency register (Register 0x08) is updated, ensuring a repeatable cutoff frequency from device to device. Although the default setting specifies that the LPF be active, it can also be bypassed providing a nominal f Table 20 shows the SPI registers pertaining to the LPF ...
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... Alternative power bias settings are also available via Register 0x13 o as discussed in the Power Control and Dissipation section. et Lastly, the ADC can be completely powered down for half- duplex operation, further reducing the AD9866’s peak powe consumption. 192 208 240 224 ...
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... AD9866 AGC TIMING CON SIDE RA TIONS W hen implementing a digital AGC timing loop important to consider the Rx path latency and settling ti in response to a change in gain setting. Fi show the RxPGA’s settling response and 5 dB change in gain setting when using the Tx[5:0] or PGA[5:0] port. While the RxPGA settling time may also show a slight dependency on the LPF’ ...
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... DATA OSCIN Note: if the reference frequency appearing at OSCIN is chosen to be equal to the AD9866’s Tx and Rx path’s word rate, then M is simply equal to log (F). 2 The clock source for the ADC can be selected in Register 0x04 as a buffered version of the reference frequency appearing at ...
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... AD9866 CLKOUT2 is a divided version of the reference frequency, f and can be set submultiple integer of f where 2). With L set to 0, the output of CLKOUT2 is a delayed version of the signal appearing at OSCIN, exhibiting the same duty cycle characteristics. With L set the ...
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... Significant power savings can be realized in applications having a half-duplex protocol allowing only the path to be operational at any instance. The power savings method depends on whether the AD9866 is configured for a full- or half-duplex interface. Functional blocks having fast power on/off times for the Tx and Rx path are controlled by the following bits: TxDAC/IAMP, TX Digital, ADC, and RxPGA ...
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... To disable the fast power-down of the Tx and/or Rx circuitry, set Bit 1 and/or Bit POWER REDUCTION OPTIONS The power consumption of the AD9866 can be significantly reduced from its default setting by optimizing the power consumption vs. performance of the various functional blocks in the Tx and Rx signal path. On the Tx path, minimum power consumption is realized when the TxDAC output is used directly and its standing current reduced to as low ...
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... ADC SAMPLE RATE (MSPS) SNR-00 SNR-01 SNR-10 SNR-11 THD-00 THD-01 THD-10 THD- SAMPLE RATE (MSPS) and SPGA Bias Setting with ADC = 10 MHz. AIN = −1 dBFS RxPGA = 0 dB AD9866 70 80 –54 –56 –58 –60 –62 –64 –66 –68 –70 –72 –74 80 ...
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... Rx path using an input waveform that is representative of the application. POWER DISSIPATION The power dissipation of the AD9866 can become quite high in full-duplex applications in which the Tx and Rx paths are si- multaneously operating with nominal power bias settings. In fact, some applications that use the IAMP may need to either reduce its peak power capabilities or reduce the power con- sumption of the Rx path, so that the device’ ...
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... A hardware ( RESET pin) or software (Bit 5 of Register 0x00) reset can be used to place the AD9866 into a known state of operation as determined by the state of the MODE and CONFIG pins offset calibration and filter tuning routine is also initiated upon a hardware reset, but not with a software reset. ...
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... MxFE. The AD9866 has several pins that are used to decouple sensitive internal nodes. These pins are REFIO, REFB, and REFT. The decoupling capacitors connected to these points should have low ESR and ESL ...
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... MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the MxFE further reduces the possibility of noise corrupting these signals. Rev Page AD9866 ...
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... AD9866 EVALUATION BOARD An evaluation board is available for the AD9865 and AD9866. The digital interface to the evaluation board can be configured for a half- or full-duplex interface. Two 40-pin and one 26-pin male right angle headers (0.100 inches) provide easy interfacing to test equipment such as digital data capture boards, pattern generators, or custom digital evaluation boards (FPGA, DSP, or ASIC) ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Rev Page PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-64-3 CP-64-3 AD9866 ...
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... AD9866 NOTES ©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04560-0-8/11(B) Rev Page ...