AD9866 Analog Devices, AD9866 Datasheet - Page 25

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

To add flexibility to the full-duplex digital interface port, several
programming options are available in the SPI registers. These
options are listed in Table 14. The timing for the Tx[5:0] and/or
Rx[5:0] ports can be independently changed by selecting either
the rising or falling clock edge as the sampling/validating edge of
the clock. Inverting RXCLK (via Bit 1 or Register 0x05) affects
both the Rx and Tx interface, because they both use RXCLK.
Table 14. SPI Registers for Full-Duplex Interface
Address (Hex)
0x05
0x0B
0x0C
0x0D
0x0E
The default Tx and Rx data input formats are twos complement,
but can be changed to straight binary. The default TXSYNC and
RXSYNC settings can be changed such that the first nibble of
the word appears while TXSYNC, RXSYNC, or both are high.
Also, the least significant nibble can be selected as the first
nibble of the word (LS nibble first). The output driver strength
can also be reduced for lower data rate applications.
RXSYNC
RXCLK
Rx[5:0]
Rx0LSB
Figure 54. Full-Duplex Rx Port Timing
Rx1MSB
t
DV
Bit
(2)
(1)
(0)
(2)
(4)
(3)
(2)
(1)
(0)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
Rx1LSB
Description
OSCIN to RXCLK
Disable RXCLK
Rx gain on Tx port
LS nibble first
TXCLK negative edge
Twos complement
Rx port three-state
LS nibble first
RXCLK negative edge
Twos complement
Low drive strength
Invert RXCLK
Invert TXSYNC
NA
Invert RXSYNC
NA
Rx2MSB
t
DH
Rx2LSB
Rx3MSB
Rev. B | Page 25 of 48
Figure 55 shows a possible digital interface between an ASIC
and the AD9866. The AD9866 serves as the master generating
the required clocks for the ASIC. This interface requires that the
ASIC reserve 16 pins for the interface, assuming a 6-bit nibble
width and the use of the Tx port for RxPGA gain control. Note
that the ASIC pin allocation can be reduced by 3, if a 5-bit nibble
width is used and the gain (or gain strobe) of the RxPGA is
controlled via the SPI port.
DIGITAL ASIC
Rx Data[5:0]
Tx Data[5:0]
RX_SYNC
TX_SYNC
Figure 55. Example of a Full-Duplex Digital Interface
CLKIN
with Optional RxPGA Gain Control via Tx[5:0]
OPTIONAL
FROM
CRYSTAL
OR MASTER CLK
Tx[5:0]
GAIN
RXSYNC
TXSYNC
RXCLK
CLKOUT1
CLKOUT2
OSCIN
Rx[5:0]
AD9865/AD9866
10/12
10/12
6
AD9866
TO
RxPGA
TO
Tx DIGITAL
FILTER
FROM
RxADC