AD9866 Analog Devices, AD9866 Datasheet - Page 36

• Manufacturer Part Number: AD9866
• Manufacturer: Analog Devices

Specifications of AD9866

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Nibble
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9866
AGC
W
to consider the Rx path latency and settling ti
in response to a change in gain setting. Fi
show the RxPGA’s settling response to a 60 dB and 5 dB change
in gain setting when using the Tx[5:0] or PGA[5:0] port. While
the RxPGA settling time may also show a slight dependency on
the LPF’s cutoff frequency, the ADC’s pipeline delay along with
the ADIO bus interface presents a more significant delay. The
hen implementing a digital AGC timing loop, it is important
TIMING CON
SIDE
RA
TIONS
gure 21 and Figure 24
me of the Rx path
Rev. B | Page 36 of 48
amount of delay or latency depends on whether a half- or full-
duplex is selected. An impulse response at the RxPGA’s input
can be observed after 10.0 ADC clock cycles (1/f
of a half-duplex interface and 10.5 ADC clock cycles in the cas
of a full-duplex interface. This latency along with the RxPGA
settling time should be considered to ensure stability of the
AGC loop.
ADC
) in the case
e