SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 519

• Manufacturer Part Number: SAM9X35
• Manufacturer: Atmel Corporation

Specifications of SAM9X35

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.7.18
Name:
Address:
Access:
Reset:
This register can only be written if the WPEN bit is cleared in
• SRC_PER
Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.
• DST_PER
Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.
• SRC_REP
0 (CONTIGUOUS_ADDR): When automatic mode is activated, source address is contiguous between two buffers.
1 (RELOAD_ADDR): When automatic mode is activated, the source address and the control register are reloaded from
previous transfer.
• SRC_H2SEL
0 (SW): Software handshaking interface is used to trigger a transfer request.
1 (HW): Hardware handshaking interface is used to trigger a transfer request.
• DST_REP
0 (CONTIGUOUS_ADDR): When automatic mode is activated, destination address is contiguous between two buffers.
1 (RELOAD_ADDR): When automatic mode is activated, the destination and the control register are reloaded from the pre-
vious transfer.
• DST_H2SEL
0 (SW): Software handshaking interface is used to trigger a transfer request.
1 (HW): Hardware handshaking interface is used to trigger a transfer request.
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
31
23
15
–
–
–
7
DMAC Channel x [x = 0..7] Configuration Register
DMAC_CFGx [x = 0..7]
0xFFFFEC50 (0)[0], 0xFFFFEC78 (0)[1], 0xFFFFECA0 (0)[2], 0xFFFFECC8 (0)[3], 0xFFFFECF0 (0)[4],
0xFFFFED18 (0)[5], 0xFFFFED40 (0)[6], 0xFFFFED68 (0)[7], 0xFFFFEE50 (1)[0], 0xFFFFEE78 (1)[1],
0xFFFFEEA0 (1)[2], 0xFFFFEEC8 (1)[3], 0xFFFFEEF0 (1)[4], 0xFFFFEF18 (1)[5], 0xFFFFEF40 (1)[6],
0xFFFFEF68 (1)[7]
Read-write
0x0100000000
LOCK_IF_L
30
22
14
–
–
6
DST_PER
DST_H2SEL
LOCK_B
29
21
13
5
FIFOCFG
DST_REP
LOCK_IF
28
20
12
4
“DMAC Write Protect Mode
27
19
11
–
–
–
3
26
18
10
–
–
2
SRC_PER
Register”.
SRC_H2SEL
AHB_PROT
25
17
–
9
1
SAM9X35
SAM9X35
SRC_REP
SOD
24
16
8
0
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