SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 500
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 500 of 1325
- Download datasheet (30Mb)
31.7
Table 31-4.
500
500
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C+ch_num*(0x28)+(0x0)
0x03C+ch_num*(0x28)+(0x4)
0x03C+ch_num*(0x28)+(0x8)
0x03C+ch_num*(0x28)+(0xC)
0x03C+ch_num*(0x28)+(0x10)
0x03C+ch_num*(0x28)+(0x14)
0x03C+ch_num*(0x28)+(0x18)
0x03C+ch_num*(0x28)+(0x1C)
0x03C+ch_num*(0x28)+(0x20)
0x03C+ch_num*(0x28)+(0x24)
0x1E4
0x1E8
0x01EC- 0x1FC
DMA Controller (DMAC) User Interface
SAM9X35
SAM9X35
Register Mapping
Register
DMAC Global Configuration Register
DMAC Enable Register
DMAC Software Single Request Register
DMAC Software Chunk Transfer Request Register
DMAC Software Last Transfer Flag Register
Reserved
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Enable register.
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Disable register.
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Mask Register.
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Status Register.
DMAC Channel Handler Enable Register
DMAC Channel Handler Disable Register
DMAC Channel Handler Status Register
Reserved
Reserved
DMAC Channel Source Address Register
DMAC Channel Destination Address Register
DMAC Channel Descriptor Address Register
DMAC Channel Control A Register
DMAC Channel Control B Register
DMAC Channel Configuration Register
DMAC Channel Source Picture in Picture Configuration
Register
DMAC Channel Destination Picture in Picture Configuration
Register
Reserved
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Name
DMAC_GCFG
DMAC_EN
DMAC_SREQ
DMAC_CREQ
DMAC_LAST
DMAC_EBCIER
DMAC_EBCIDR
DMAC_EBCIMR
DMAC_EBCISR
DMAC_CHER
DMAC_CHDR
DMAC_CHSR
–
–
DMAC_SADDR
DMAC_DADDR
DMAC_DSCR
DMAC_CTRLA
DMAC_CTRLB
DMAC_CFG
DMAC_SPIP
DMAC_DPIP
–
–
DMAC_WPMR
DMAC_WPSR
–
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Write-only
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
–
Read-write
–
Read-only
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
Reset
0x10
0x0
0x0
0x0
0x0
–
–
0x0
0x0
–
–
0x00FF0000
–
–
0x0
0x0
0x0
0x0
0x0
0x01000000
0x0
0x0
–
–
0x0
0x0
–
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