SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 1311

• Manufacturer Part Number: SAM9X35
• Manufacturer: Atmel Corporation

Specifications of SAM9X35

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Revision History
11055B–ATARM–22-Sep-11
Doc. Rev.
11055B
Doc. Rev.
11055A
Comments
System Controller:
Figure
ADC:
Section 42. “Analog-to-Digital Converter (ADC)”
DMAC:
FIFO size table removed from
“DMA Controller
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment
PMC:
Section 22.2 “Embedded
Then
Figure
Section 22.3 “Master Clock
Section 22.7 “LP-DDR/DDR2
Section 22.13.11 “PMC Master Clock
UHPHS:
“OHCI”
sentence.
Electrical Characteristics:
Section 47.12 “USB Transceiver Characteristics”
41-23 and Table 41-46).
Errata:
Section 50.1 “Boot Sequence Controller (BSC)”
programmer description.
Section 50.5 “USB High Speed Host Port (UHPHS)” removed.
Comments
1st issue
- Prescaler /1,/2,/4,.../64 --> Prescaler /1,/2,/3,/4,.../64 (for Master Clock Controller).
- SysClk DDR --> 2x MCK, and connection added above with /2 block and DDRCK.
- Value 7 for PRES field no more reserved, now with CLOCK_DIV3, Selected clock divided by 3.
- MDIV field, references to ‘SysClk DDR’ removed (x4).
DDR system clock --> DDR clock.
7-1,
22-2,
,
Figure 32-2 “Board Schematics to Interface UHP Device Controller”
“SAM9X35 System Controller Block Diagram”
“General Clock Block Diagram”
0”) and DMAC1 (see
In the tables that follow, the most recent version appears first. “rfo” denotes expert input during
the update process
Characteristics”,
Controller”, ...and the division by 6 --> ...and the division by 3
Clock”, sentences with ‘ SysClk’ removed.
Section 31.1
Register”:
Section 31.2.2 “DMA Controller
266MHz DDR system clock --> 133MHz DDR system clock
“Description”, as the size depends on DMAC0 (see
:
Register”, description of NFD0_ON_D16 bitfield updated.
updated to show Touchscreen information
added as the BSC_CR register does not conply with the
added (extracted from SAM9G20 - 6384E: Section 41.7, Figure
, DDR sysclk --> DDRCK.
1”)
added, with an introducing
Section 31.2.1
SAM9X35
Change
Request
Ref.
rfo
7987
8004
8008
7975
rfo
7974
8006
8016
8016
7996
rfo
Change
Request
Ref.
1309