SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 23

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SAM9G20

Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G20

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
8.2.4
9. System Controller
6384DS–ATARM–13-Jan-10
Error Corrected Code Controller
The System Controller is a set of peripherals, which allow handling of key elements of the sys-
tem, such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface embeds also the registers allowing to configure the Matrix
and a set of registers for the chip configuration. The chip configuration registers allows
configuring:
The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address
space, between addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All
the registers of the System Controller can be addressed from a single pointer by using the stan-
dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes.
Figure 9-1 on page 24
Figure 8-1 on page 19
peripherals.
• Programming facilities
• Energy-saving capabilities
• Error detection
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
• Hardware Error Corrected Code (ECC) Generation
• Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path.
• Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes,
• Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data
• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes
• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes
Specified by Software
Path
with 8-bit Data Path
with 8-bit Data Path
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Self-refresh, power down and deep power down modes supported
– Refresh Error Interrupt
– Detection and Correction by Software
– EBI chip select assignment and Voltage range for external memories
shows the System Controller block diagram.
shows the mapping of the User Interfaces of the System Controller
AT91SAM9G20 Summary
23

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