SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 21

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1.1.1
8.1.1.2
6384DS–ATARM–13-Jan-10
BMS = 1, Boot on Embedded ROM
BMS = 0, Boot on External Memory
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
The AT91SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin
at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved
for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
The system boots using the Boot Program.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
• SAM-BA
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
4. Switch the main clock to the new value.
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
– SDCard (boot ROM does not support high capacity SDCards.)
– NAND Flash
– SPI DataFlash
– EEPROM on TWI
– Serial communication on a DBGU
– USB Device HS Port
to the new clock.
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in
®
Boot in case no valid program is detected in external NVM, supporting
®
and Serial Flash connected on NPCS0 and NPCS1 of the SPI0
AT91SAM9G20 Summary
Figure 8-1 on page
19.
21