SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 14
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
6. I/O Line Considerations
6.1
6.2
6.3
6.4
6.5
6.6
14
JTAG Port Pins
Test Pin
Reset Pins
PIO Controllers
I/O Line Drive Levels
Shutdown Logic Pins
AT91SAM9G20 Summary
TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
The NTRST signal is described in the Reset Pins paragraph.
All the JTAG signals are supplied with VDDIOP.
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 kΩ minimum to
VDDIOP.
The NRST signal is inserted in the Boundary Scan.
All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers inte-
grate a programmable pull-up resistor of 75 kΩ typical with the exception of P4 - P31. For details,
refer to the section “AT91SAM9G20 Electrical Characteristics”. Programming of this pull-up
resistor is performed independently for each I/O line through the PIO Controllers.
The PIO lines drive current capability is described in the DC Characteristics section of the prod-
uct datasheet.
The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is
no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1
MΩ. The resisitor value is calculated according to the regulator enable implementation and the
SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
6384DS–ATARM–13-Jan-10