SAM3N2B Atmel Corporation, SAM3N2B Datasheet - Page 490

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SAM3N2B

Manufacturer Part Number
SAM3N2B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N2B

Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
28.10.6
Figure 28-32. Read Write Flowchart in Slave Mode
490
490
SAM3N
SAM3N
Read Write Flowcharts
No
No
SADR + MSDIS + SVEN
Set the SLAVE mode:
Read Status Register
EOSACC = 1 ?
TXCOMP = 1 ?
SVACC = 1 ?
No
END
The flowchart shown in
in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt
method requires that the interrupt enable register (TWI_IER) be configured first.
GACC = 1 ?
Figure 28-32 on page 490
No
programming sequence
Read TWI_RHR
SVREAD = 0 ?
RXRDY= 0 ?
Decoding of the
Change SADR
Prog seq
OK ?
No
gives an example of read and write operations
No
GENERAL CALL TREATMENT
No
Write in TWI_THR
TXRDY= 1 ?
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
No

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