SAM3N2B Atmel Corporation, SAM3N2B Datasheet - Page 438

• Manufacturer Part Number: SAM3N2B
• Manufacturer: Atmel Corporation

Specifications of SAM3N2B

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 27-8. PDC Status Register Flags Behavior
27.7.3.3
27.7.3.4
438
438
(from master)
(from slave)
TXEMPTY
SAM3N
SAM3N
RXBUFF
TXBUFE
ENDRX
ENDTX
NPCS0
SPCK
MOSI
MISO
Clock Generation
Transfer Delays
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1
and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating
baud rate of MCK divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead
to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the
SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud
rate for each interfaced peripheral without reprogramming.
Figure 27-9
select. Three delays can be programmed to modify the transfer waveforms:
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
• The delay between chip selects, programmable only once for all the chip selects by writing
• The delay before SPCK, independently programmable for each chip select by writing the field
• The delay between consecutive transfers, independently programmable for each chip select
MSB
the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on
the same chip select
MSB
6
6
5
5
shows a chip select transfer change and consecutive transfers on the same chip
4
4
1
3
3
2
2
1
1
LSB
LSB
MSB
MSB
6
6
5
5
4
4
2
3
3
2
2
1
1
LSB
LSB
MSB
MSB
6
6
5
5
3
4
4
3
3
2
2
1
1
LSB
LSB
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10