SAM3N2B Atmel Corporation, SAM3N2B Datasheet - Page 440

• Manufacturer Part Number: SAM3N2B
• Manufacturer: Atmel Corporation

Specifications of SAM3N2B

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.7.3.7
440
440
Transfer Size
SAM3N
SAM3N
Peripheral Chip Select Decoding
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data
to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit
wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how-
ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI
lines with the chip select configuration registers. This is not the optimal means in term of mem-
ory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the
type of pointer's size it has to point to. The PDC will perform the following transfer size depend-
ing on the mode and number of bits per data.
Fixed Mode:
Variable Mode:
In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for
8 to 16-bit transfer size. When using the PDC, the TDRE and RDRF flags are handled by the
PDC, thus the user’s application does not have to check those bits. Only End of RX Buffer
(ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty (TXBUFE) are
significant. For further details about the Peripheral DMA Controller and user interface, refer to
the PDC section of the product datasheet.
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by
writing the PCSDEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field,
only the lowest numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on
NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when
not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
an implementation.
• 8-bit Data:
• 8-bit to 16-bit Data:
Byte transfer,
PDC Pointer Address = Address + 1 byte,
PDC Counter = Counter - 1
2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC Pointer Address = Address + 2 bytes,
PDC Counter = Counter - 1
Figure 27-10
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
below shows such