SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 643

• Manufacturer Part Number: SAM3N2A
• Manufacturer: Atmel Corporation

Specifications of SAM3N2A

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.7
Name:
Address:
Access:
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
32.7.8
Name:
Address:
Access:
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
11011A–ATARM–04-Oct-10
31
23
15
31
23
15
7
7
PWM Interrupt Mask Register
PWM Interrupt Status Register
30
22
14
30
22
14
0x40020018
6
0x4002001C
6
PWM_IMR
Read-only
PWM_ISR
Read-only
29
21
13
29
21
13
5
5
28
20
12
28
20
12
4
4
CHID3
CHID3
27
19
11
27
19
11
3
3
CHID2
CHID2
26
18
10
26
18
10
2
2
CHID1
CHID1
25
17
25
17
9
1
9
1
SAM3N
CHID0
CHID0
24
16
24
16
8
0
8
0
643