SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 152
SAM3N2A
Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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SAM3N
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-
ters. For more information see the description of the NVIC_SetPriority function in
programming hints” on page
onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt.
Table 10-28. Mapping of interrupts to the interrupt variables
1.
Interrupts
0-32
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the
array IP[0] to IP[32] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds
the interrupt priority for interrupt n.
Each array element corresponds to a single NVIC register, for example the element
ICER[0] corresponds to the ICER0 register.
CMSIS array elements
Set-enable
ISER[0]
Clear-enable
ICER[0]
163.
Table 10-28
(1)
Set-pending
ISPR[0]
shows how the interrupts, or IRQ numbers, map
Clear-pending
ICPR[0]
Active Bit
IABR[0]
11011A–ATARM–04-Oct-10
“NVIC
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