SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 364

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SAM3N2A

Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N2A

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
24.15.10 PMC Master Clock Register
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLDIV2: PLL Divisor by 2
364
31
23
15
7
PLLDIV2
SAM3N
Value
Value
0
1
2
3
0
1
2
3
4
5
6
7
0
1
PMC_MCKR
0x400E0430
Read-write
30
22
14
6
Name
SLOW_CLK
MAIN_CLK
PLL_CLK
Name
CLK
CLK_2
CLK_4
CLK_28
CLK_16
CLK_32
CLK_64
CLK_3
PLL Clock Division
PLL clock frequency is divided by 1
PLL clock frequency is divided by 2
PRES
29
21
13
5
PLLDIV2
28
20
12
4
Slow Clock is selected
Main Clock is selected
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Selected clock divided by 3
Description
PLL Clock is selected
Reserved
“PMC Write Protect Mode Register” on page
27
19
11
3
26
18
10
2
25
17
9
1
11011A–ATARM–04-Oct-10
CSS
374.
24
16
8
0

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