ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 83

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.8
8291A–AVR–10/11
PLL and External Clock Source Failure Monitor
The value that should be written to the COMP register is given by the following formula:
When the DFLL is enabled, it controls the ratio between the reference clock frequency and the
oscillator frequency. If the internal oscillator runs too fast or too slow, the DFLL will decrement or
increment its calibration register value by one to adjust the oscillator frequency. The oscillator is
considered running too fast or too slow when the error is more than a half calibration step size.
Figure 7-7.
The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake
up, the DFLL will continue with the calibration value found before entering sleep. The reset value
of the DFLL calibration register can be read from the production signature row.
When the DFLL is disabled, the DFLL calibration register can be written from software for man-
ual run-time calibration of the oscillator.
A built-in failure monitor is available for the PLL and external clock source. If the failure monitor
is enabled for the PLL and/or the external clock source, and this clock source fails (the PLL
looses lock or the external clock source stops) while being used as the system clock, the device
will:
If the PLL or external clock source fails when not being used for the system clock, it is automati-
cally disabled, and the system clock will continue to operate normally. No NMI is issued. The
• Switch to run the system clock from the 2MHz internal oscillator
• Reset the oscillator control register and system clock selection register to their default values
• Set the failure detection interrupt flag for the failing clock source (PLL or external clock)
• Issue a non-maskable interrupt (NMI)
DFLL CNT
clk
COMP
RCnCREF
Automatic run-time calibration.
0
COMP =
Frequency
OK
t
RCnCREF
hex
CALA decremented
(
f
RCOSC fast,
f
RCnCREF
RCOSC
Atmel AVR XMEGA B
)
CALA incremented
RCOSC slow,
83