ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 226

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.13.7
18.13.8
18.13.9
8291A–AVR–10/11
EPPTRL – Endpoint Configuration Table Pointer Low Byte
EPPTRH – Endpoint Configuration Table Pointer High byte
INTCTRLA – Interrupt Control register A
The EPPTRL and EPPTRH registers represent the 16-bit value, EPPTR, that contains the
address to the endpoint configuration table. The pointer to the endpoint configuration table must
be aligned to a 16-bit word; i.e., EPPTR[0] must be zero. Only the number of bits required to
address the available internal SRAM memory is implemented for each device. Unused bits will
always be read as zero.
• Bit 7:0 – EPPTR[7:0]: Endpoint Configuration Table Pointer
This register contains the eight lsbs of the endpoint configuration table pointer (EPPTR).
• Bit 7:0 – EPPTR[15:8]: Endpoint Configuration Table Pointer
This register contains the eight msbs of the endpoint configuration table pointer (EPPTR).
• Bit 7 – SOFIE: Start Of Frame Interrupt Enable
Setting this bit enables the start of frame (SOF) interrupt for the conditions that set the start of
frame interrupt flag (SOFIF) in the INTFLAGSACLR/ INTFLAGSASET register. The INTLVL bits
must be nonzero for the interrupts to be generated.
• Bit 6 – BUSEVIE: Bus Event Interrupt Enable
Setting this bit will enable the interrupt for the following three bus events:
The INTLVL bits must be nonzero for the interrupts to be generated.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x07
Read/Write
Initial Value
1. Suspend: An interrupt will be generated for the conditions that set the suspend interrupt
2. Resume: An interrupt will be generated for the conditions that set the resume interrupt
3. Reset: An interrupt will be generated for the conditions that set the reset interrupt flag
flag (SUSPENDIF) in the INTFLAGSACLR/SET register.
flag (RESUMEIF) in the INTFLAGSACLR/SET register.
(RESETIF) in the INTFLAGSACLR/SET register.
SOFIE
R/W
R/W
R/W
7
0
7
0
7
0
BUSEVIE
R/W
R/W
R/W
6
0
6
0
6
0
BUSERRIE
R/W
R/W
R/W
5
0
5
0
5
0
STALLIE
R/W
R/W
R/W
4
0
4
0
4
0
EPPTR[15:8]
EPPTR[7:0]
R/W
R/W
3
0
3
0
R
3
–
0
Atmel AVR XMEGA B
R/W
R/W
2
0
2
0
R
2
–
0
R/W
R/W
R/W
1
0
1
0
1
0
INTLVL[1:0]
R/W
R/W
R
0
0
0
0
0
0
INTCTRLA
EPPTRH
EPPTRL
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