ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 303
ATxmega128B3
Manufacturer Part Number
ATxmega128B3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.2.5
24.3
8291A–AVR–10/11
Block Diagram
Minimizing Power Consumption
A start of new frame triggers an update of the Shadow Display Memory. The content of Display
Memory is saved into the Shadow Display Memory. A Display Memory refresh is possible with-
out affecting data that is sent to the panel.
When a bit in the Display Memory is written to one, the corresponding segment will be energized
(“ON”), and de-energized (“OFF”) when this bit is written to zero.
To energize a segment, an absolute voltage above a certain threshold must be applied. This is
done by setting the SEG pin to opposite phase when the corresponding COM pin is active. For a
display with more than one common terminal, two (1/3 bias) additional voltage levels must be
applied. Otherwise, non-energized segments on COM0 would be energized for all non-selected
common terminals.
Addressing COM0 starts a frame by driving an opposite phase with large amplitude on COM0 as
against non addressed COM lines. Non-energized segments are in phase with the addressed
COM0, and energized segments have opposite phase and large amplitude. For waveform fig-
ures refer to
DATA4 - DATA0 from Shadow Display Memory is multiplexed into the decoder. The decoder is
controlled from the LCD timing and sets up signals controlling the analog switches to produce an
output waveform.
Next, COM1 is addressed, and DATA9 - DATA5 from Shadow Display Memory is input to the
decoder. Addressing continues until all COM lines are addressed according to the number of
selected common terminals (duty).
The power consumption of the LCD controller can be minimized by:
Figure 24-2. LCD Controller Block Diagram
1.
2.
3.
Using the lowest acceptable frame rate - Refer to the LCD glass technical characteristics.
Using the low power waveform -
Programming the lowest possible contrast value -
”Mode of Operation” on page
Character
Mapping
Memory
Display
CTRLG
CTRLH
DATAn
DATA0
DATA1
:
CTRLB
CTRLD
CTRLE
Timing
CTRLF
”Low Power Waveform” on page 306
Shadow
Memory
Display
304.
LCD Power
CTRLA
CTRLC
CAPH CAPL
Supply
Control & Swap
”CTRLF – Control Register F” on page 315.
Atmel AVR XMEGA B
Analog
Switch
Array
INT
V
BIAS
BIAS
LCD
SEGx
COMy
1
2
303
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