ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 162

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.8.4
8291A–AVR–10/11
Dual-slope PWM
Figure 13-15. Single-slope pulse width modulation.
The PER register defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003),
and the maximum resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for single-slope PWM (R
The single-slope PWM frequency (f
eral clock frequency (fclk
where N represents the prescaler divider used. The waveform generated will have a maximum
frequency of half of the peripheral clock frequency (fclk
and no prescaling is used. This also applies when using the hi-res extension, since this
increases the resolution and not the frequency.
For dual-slope PWM generation, the period (T) is controlled by PER, while CCx registers control
the duty cycle of the WG output.
counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. The waveform gener-
ator output is set on BOTTOM, cleared on compare match when up-counting, and set on
compare match when down-counting.
R
f
PWM_SS
CNT
WG Output
PWM_SS
=
=
BOTTOM
log
---------------------------------- -
------------------------------ -
N PER
(
MAX
TOP
fclk
(
log
PER
PER
CCx
2 ( )
+
+
1
1
)
)
PER
Period (T)
), and can be calculated by the following equation:
Figure 13-16
PWM_SS
) depends on the period setting (PER) and the periph-
CCx=BOTTOM
shows how for dual-slope PWM the counter
Atmel AVR XMEGA B
PER
) when CCA is set to zero (0x0000)
CCx=TOP
PWM_SS
"update"
"match"
):
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