ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 94
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ATtiny88
Manufacturer Part Number
ATtiny88
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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12.5
94
Counter Unit
ATtiny48/88
located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and
prescaler, see
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 12-2
Figure 12-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT1H value when the TCNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS1[2:0]). When no clock source is selected (CS1[2:0] = 0)
the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clk
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM1[3:0]) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
Count
Direction
Clear
clk
TOP
BOTTOM
T
1
TCNTnH (8-bit)
TEMP (8-bit)
T
shows a block diagram of the counter and its surroundings.
1
is present or not. A CPU write overrides (has priority over) all counter clear or
“Timer/Counter0 and Timer/Counter1 Prescalers” on page
TCNTn (16-bit Counter)
DATA BUS
T
1
). The clk
TCNTnL (8-bit)
(8-bit)
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock.
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
T
1
can be generated from an external or internal clock source,
Direction
Count
Clear
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
117.
8008H–AVR–04/11
Tn