ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 127
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ATtiny88
Manufacturer Part Number
ATtiny88
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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14.5.2
8008H–AVR–04/11
SPSR – SPI Status Register
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 14-4.
• Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the oscillator clock frequency f
shown in the following table:
Table 14-5.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bits 5:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit
0x2D (0x4D)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
CPHA
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
SPIF
R
7
0
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
R
5
–
0
Figure 14-3
Leading Edge
Sample
Setup
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
and
R
3
–
0
Figure 14-4
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
for an example. The CPOL
R
1
–
0
Trailing Edge
ATtiny48/88
Sample
Setup
SPI2X
R/W
0
0
SPSR
osc
127
is