ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 61
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATtiny88
Manufacturer Part Number
ATtiny88
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATtiny88-12AU
Manufacturer:
ATMEL
Quantity:
2 165
Company:
Part Number:
ATtiny88-15AZ
Manufacturer:
Atmel
Quantity:
7 370
Company:
Part Number:
ATtiny88-15MZ
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATtiny88-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny88-AU
Manufacturer:
ATMEL
Quantity:
5 000
Company:
Part Number:
ATtiny88-AU
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATtiny88-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny88-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny88-MUR
Manufacturer:
AT
Quantity:
20 000
10.2
10.2.1
8008H–AVR–04/11
Ports as General Digital I/O
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
77, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
D
L
Q
Q
D
PINxn
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
Figure 10-2
RRx
ATtiny48/88
PUD
WDx
RDx
RPx
clk
1
0
I/O
WRx
shows a func-
WPx
“Register
I/O
,
61