ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 159

• Manufacturer Part Number: ATtiny88
• Manufacturer: Atmel Corporation

Specifications of ATtiny88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.11.4
15.11.5
8008H–AVR–04/11
TWDR – TWI Data Register
TWAR – TWI (Slave) Address Register
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 15-7.
To calculate bit rates, see
in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
Bit
(0xBB)
Read/Write
Initial Value
Bit
(0xBA)
Read/Write
Initial Value
TWPS1
0
0
1
1
TWI Bit Rate Prescaler
TWD7
TWA6
R/W
R/W
7
1
7
1
TWD6
TWA5
R/W
R/W
“Bit Rate Generator Unit” on page
TWPS0
0
1
0
1
6
1
6
1
TWD5
TWA4
R/W
R/W
5
1
5
1
TWD4
TWA3
R/W
R/W
4
1
4
1
Prescaler Value
1
4
16
64
TWD3
TWA2
R/W
R/W
3
1
3
1
135. The value of TWPS1:0 is used
TWD2
TWA1
R/W
R/W
2
1
2
1
TWD1
TWA0
R/W
R/W
1
1
1
1
ATtiny48/88
TWGCE
TWD0
R/W
R/W
0
1
0
0
TWDR
TWAR
159