ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 210

• Manufacturer Part Number: ATtiny87
• Manufacturer: Atmel Corporation

Specifications of ATtiny87

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11.6
17.11.7
210
ATtiny87/ATtiny167
DIDR1 – Digital Input Disable Register 1
AMISCR – Analog Miscellaneous Control Register
• Bits 7:0 – ADC7D:ADC0D: ADC[7:0] Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When
an analog signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to
zero when DIDR1 register is written.
• Bits 6:4 – ADC10D, ADC9D, ADC8D: ADC[10:8] Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When
an analog signal is applied to the ADC10:8 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
• Bits 3:0 - Res: Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be writ-
ten to zero when DIDR1 is written.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be writ-
ten to zero when AMISCR is written.
• Bit 2 – AREFEN: External Voltage Reference Input Enable
When this bit is written logic one, the voltage reference for the ADC is input from AREF pin as
described in
AREF higher than (AV
internal voltage reference options may not be used if an external voltage is being applied to
the AREF pin. It is recommended to use DIDR register bit function (digital input disable) when
AREFEN is set.
• Bit 1 – XREFEN: Internal Voltage Reference Output Enable
When this bit is written logic one, the internal voltage reference 1.1V or 2.56V is output on
XREF pin as described in
bit function (digital input disable) when XREFEN is set.
Bit
(0x7F)
Read/Write
Initial Value
Bit
(0x77)
Read/Write
Initial Value
Table 17.10 on page
R
R
7
–
0
7
–
0
ADC10D
CC
R/W
6
0
R
6
–
0
- 1V) is not recommended, as this will affect ADC accuracy. The
Table 17.10 on page
ADC9D
R/W
203. If active channels are used, using AV
5
0
R
5
–
0
ADC8D
R/W
R
4
0
4
–
0
203. It is recommended to use DIDR register
R
R
3
–
0
3
–
0
AREFEN
R/W
R
2
–
0
2
0
XREFEN
R/W
R
1
–
0
1
0
ISRCEN
CC
R/W
R
0
–
0
0
0
or an external
8265B–AVR–09/10
AMISCR
DIDR1