ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 129

• Manufacturer Part Number: ATtiny87
• Manufacturer: Atmel Corporation

Specifications of ATtiny87

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8265B–AVR–09/10
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM1[3:0] = 8), or the value in OCR1A (WGM1[3:0] = 9).
The counter has then reached the TOP and changes the count direction. The TCNT1 value
will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and
frequency correct PWM mode is shown on
quency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is
in the timing diagram shown as a histogram for illustrating the dual-slope operation. The dia-
gram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the
TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B
interrupt flag will be set when a compare match occurs.
Figure 12-10. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1A/B
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or
ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached
TOP. The interrupt flags can then be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the
OCR1A/B.
As
metrical in all periods. Since the OCR1A/B Registers are updated at BOTTOM, the length of
the rising and the falling slopes will always be equal. This gives symmetrical output pulses and
is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How-
ever, if the base PWM frequency is actively changed by changing the TOP value, using the
OCR1A as TOP is clearly a better choice due to its double buffer feature.
Figure 12-10
OCnxi
OCnxi
TCNTn
Period
shows the output generated is, in contrast to the phase correct mode, sym-
1
2
3
Figure
12-10. The figure shows phase and fre-
4
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx/TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
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