ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 173
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ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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15.5.6.3
15.5.7
15.5.7.1
8265B–AVR–09/10
Data Length
Handling LBT[5:0]
Data Length in LIN 2.1
The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and
adjusts the baud rate in a ± 2% range.
The new LBT[5:0] value will be used up to the end of the response. Then, the LBT[5:0] will be
reset to 32 for the next header.
The LINBTR register can be used to (software) re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
LDISR bit of LINBTR register is used to:
Note that the LENA bit of LINCR register is important for this handling (see
page
Figure 15-8. Handling LBT[5:0]
Section 15.4.6 “LIN Commands” on page 167
set the LRXDL[3:0] or LTXDL[3:0] fields of LINDLR register before receiving or transmitting a
response.
In the case of Tx Response the LRXDL[3:0] will be used by the hardware to count the number
of bytes already successfully sent.
In the case of Rx Response the LTXDL[3:0] will be used by the hardware to count the number
of bytes already successfully received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
• Disable the re-synchronization (for instance in the case of LIN MASTER node),
• To enable the setting of LBT[5:0] (to manually adjust the baud rate especially in the case of
• If LTXDL[3:0]=0 only the CHECKSUM will be sent,
• If LRXDL[3:0]=0 the first byte received will be interpreted as the CHECKSUM,
• If LTXDL[3:0] or LRXDL[3:0] >8, values will be forced to 8 after the command setting and
UART mode). A minimum of 8 is required for LBT[5:0] due to the sampling operation.
before sending or receiving of the first byte.
173).
=1
Write in LINBTR register
(LINCR bit 4)
LENA ?
Enable re-synch. in LIN mode
LBT[5..0] forced to 0x20
LDISR forced to 0
=0
LDISR
to write
=0
describes how to set or how are automatically
=1
Disable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
LDISR forced to 1
(LBT[5..0]
min
=8)
Figure 15-8 on
173