ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 128

• Manufacturer Part Number: ATtiny87
• Manufacturer: Atmel Corporation

Specifications of ATtiny87

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.9.5
128
ATtiny87/ATtiny167
Phase and Frequency Correct PWM Mode
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1A/B pins. Setting the COM1A/B[1:0] bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1A/B[1:0] to three (See
page
the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is gener-
ated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B
and TCNT1 when the counter increments, and clearing (or setting) the OC1A/B Register at
compare match between OCR1A/B and TCNT1 when the counter decrements. The PWM fre-
quency for the output when using phase correct PWM can be calculated by the following
equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be continuously
high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct
PWM mode (WGM1[3:0] = 8 or 9) provides a high resolution phase and frequency correct
PWM waveform generation option. The phase and frequency correct PWM mode is, like the
phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly
from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare
Output mode, the Output Compare (OC1A/B) is cleared on the compare match between
TCNT1 and OCR1A/B while upcounting, and set on the compare match while downcounting.
In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a
lower maximum operation frequency compared to the single-slope operation. However, due to
the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1A/B Register is updated by the OCR1A/B Buffer Register, (see
ure 12-9
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003),
and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in
bits can be calculated using the following equation:
133). The actual OC1A/B value will only be visible on the port pin if the data direction for
and
Figure
12-10).
R
PFCPWM
f
OCnxPCPWM
=
log
---------------------------------- -
=
(
log
TOP
--------------------------- -
2 N TOP
2 ( )
⋅
f
clk_I/O
+
⋅
1
)
8265B–AVR–09/10
Table on
Fig-