ATmega644R212 Atmel Corporation, ATmega644R212 Datasheet - Page 261

• Manufacturer Part Number: ATmega644R212
• Manufacturer: Atmel Corporation

Specifications of ATmega644R212

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

Figure 21-1. Block Diagram
8011O–AVR–07/10
TDI
TDO
TCK
TMS
CONTROLLER
M
U
X
TAP
DEVICE BOUNDARY
INSTRUCTION
BREAKPOINT
SCAN CHAIN
REGISTER
REGISTER
REGISTER
BYPASS
ID
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the
TAP controller is in reset. When programmed, the input TAP signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this
fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
(Scan Chains).
DECODER
ADDRESS
JTAG PROGRAMMING
MEMORY
FLASH
AND CONTROL
BREAKPOINT
OCD STATUS
INTERFACE
UNIT
Address
Data
I/O PORT 0
I/O PORT n
INTERNAL
FLOW CONTROL
CHAIN
SCAN
UNIT
BOUNDARY SCAN CHAIN
PC
Instruction
JTAG / AVR CORE
COMMUNICATION
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
ATmega164P/324P/644P
PERIPHERIAL
ANALOG
UNITS
Control & Clock lines
Analog inputs
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