ATmega644R212 Atmel Corporation, ATmega644R212 Datasheet - Page 139

• Manufacturer Part Number: ATmega644R212
• Manufacturer: Atmel Corporation

Specifications of ATmega644R212

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
14.1
14.2
8011O–AVR–07/10
Features
Overview
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Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-12.. For the actual
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The Power Reduction Timer/Counter2 bit, PRTIM2, in
page 48
Figure 14-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
must be written to zero to enable Timer/Counter2 module.
Status flags
”Register Description” on page
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
”Pin Configurations” on page
Direction
Count
ASSRn
Clear
Synchronized Status flags
Control Logic
TOP
=
TCCRnB
asynchronous mode
Value
BOTTOM
Fixed
TOP
select (ASn)
clk
=
Tn
0
152.
ATmega164P/324P/644P
Prescaler
Synchronization Unit
OCnA
(Int.Req.)
OCnB
(Int.Req.)
Generation
Generation
2. CPU accessible I/O Registers, includ-
Waveform
Waveform
”PRR – Power Reduction Register” on
TOVn
(Int.Req.)
OCnA
OCnB
Oscillator
T/C
clk
I/O
clk
clk
I/O
ASY
TOSC1
TOSC2
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