ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 312
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ATmega32M1
Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32M1
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega32M1-15AD
Manufacturer:
ATMEL
Quantity:
1 448
Part Number:
ATmega32M1-15AD
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega32M1-AU
Manufacturer:
TYCO
Quantity:
210
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28.7
28.8
312
PLL Characteristics
SPI Timing Characteristics
ATmega16M1/32M1/64M1
Table 28-6.
.
Table 28-5.
Note:
See
Note:
Symbol
PLL
PLL
PLL
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 28-3 on page 313
IF
F
LT
While connected to external clock or external oscillator, PLL Input Frequency must be selected to
provide outputs with frequency in accordance with driven parts of the circuit (CPU core, PSC...)
In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
CLCL
CLCL
SS high to tri-state
SCK high/low
SCK to out high
SCK to SS high
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
SPI Timing Parameters
PLL Characteristics - V
Description
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
for f
for f
Setup
Setup
Parameter
Input Frequency
PLL Factor
Lock-in Time
Hold
Hold
CK
CK
<12MHz
>12MHz
(1)
and
Figure 28-4 on page 313
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
CC
= 2.7V to 5.5V (unless otherwise noted)
4 × t
2 × t
Min.
10
t
20
20
ck
ck
ck
Min.
for details.
See
0.5
50% duty cycle
Table 18-7 on
page 161
0.5 × t
Typ.
3.6
10
10
10
10
15
15
10
Typ.
sck
64
1
Max.
Max.
64
1600
2
8209D–AVR–11/10
Units
Units
ns
MHz
µS
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