ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 214

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.5.13
Figure 20-13. LIN Interrupt Mapping
20.5.14
214
LINERR.6
LINERR.1
LINERR.7
LINERR.5
LINERR.4
LINERR.3
LINERR.2
LINERR.0
ATmega16M1/32M1/64M1
Interrupts
Message Filtering
LABORT
LTOERR
LOVERR
LCERR
LFERR
LSERR
LPERR
LBERR
Table 20-4.
As shown in
drive two interrupts. Each of these flags have their respective enable interrupt bit in LINENIR
register.
See
Message filtering based upon the whole identifier is not implemented. Only a status for frame
headers having 0x3C, 0x3D, 0x3E and 0x3F as identifier is available in the LINSIR register.
The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a
classic checksum (sum over the data bytes only). Software will be responsible for switching cor-
rectly the LIN13 bit to provide/check this expected checksum (the insertion of the ID field in the
computation of the CRC is set - or not - just after entering the Rx or Tx Response command).
Section 20.5.8 “xxOK Flags” on page 211
LINSIR.3
LINSIR.2
LINSIR.1
LINSIR.0
Figure
Frame Status
LIDST[2..0]
20-13, the four communication flags of the LINSIR register are combined to
100
101
110
111
0xx
LRXOK
LTXOK
LIDOK
LERR
b
b
b
b
b
LENERR
LINENIR.3
LENIDOK
LINENIR.2
and
Section 20.5.9 “xxERR Flags” on page
LENTXOK
LINENIR.1
No specific identifier
60 (0x3C) identifier
61 (0x3D) identifier
62 (0x3E) identifier
63 (0x3F) identifier
LENRXOK
Frame Status
LINENIR.0
8209D–AVR–11/10
LIN ERR
LIN IT
212.