ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 18

• Manufacturer Part Number: ATmega32M1
• Manufacturer: Atmel Corporation

Specifications of ATmega32M1

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7. Memories
7.1
7.2
18
Overview
In-System Reprogrammable Flash Program Memory
ATmega16M1/32M1/64M1
This section describes the different memories in the ATmega16M1/32M1/64M1. The AVR archi-
tecture has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega16M1/32M1/64M1 features an EEPROM Memory for data storage. All
three memory spaces are linear and regular.
The ATmega16M1/32M1/64M1 contains 16/32/64K bytes On-chip In-System Reprogrammable
Flash memory for program storage. Since all AVR instructions are 16 bits or 32 bits wide, the
Flash is organized as 16K × 16 / 32K × 16. For software security, the Flash Program memory
space is divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega16M1/32M1/64M1 Program Counter (PC) is 14 bits wide, thus addressing the 16K pro-
gram memory locations. The operation of Boot Program section and associated Boot Lock bits
for software protection are described in detail in
Programming” on page
tion on Flash programming in SPI or Parallel programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory.
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 7-1.
15.
Program Memory Map
270.
“Memory Programming” on page 287
Application Flash Section
Boot Flash Section
Program Memory
“Boot Loader Support – Read-While-Write Self-
0x0000
0x1FFF/0x3FFF/0x7FFF
contains a detailed descrip-
“Instruction Execution Tim-
8209D–AVR–11/10