ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 220

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ATmega32M1

Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega32M1

Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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20.6.5
20.6.6
220
ATmega16M1/32M1/64M1
LINBTR – LIN Bit Timing Register
LINBRR – LIN Baud Rate Register
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
• Bits 15:12 - Reserved Bits
• Bits 11:0 - LDIV[11:0]: Scaling of clk
Bit
Read/Write
Initial Value
Bit
Bit
Read/Write
Initial Value
written to zero when LINBRR is written.
UART baud rate.
– 0 = No error
– 1 = Checksum error
– 0 = no error
– 1 = Bit error
– 0 = Bit timing re-synchronization enabled (default)
– 1 = Bit timing re-synchronization disabled
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
Gives the number of samples of a bit.
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
These bits are reserved for future use. For compatibility with future devices, they must be
The LDIV value is used to scale the entering clk
LDISR
LDIV7
R/W
R/W
15
7
0
7
0
-
sample-time = (1/
LDIV6
R/W
14
R
6
0
6
0
-
-
R/(W)
LDIV5
LBT5
R/W
13
5
1
5
0
-
f
i/o
clk
R/(W)
LDIV4
LBT4
R/W
Frequency
12
4
0
i/o
4
0
-
) × (LDIV[11..0] + 1)
R/(W)
LDIV11
LBT3
LDIV3
R/W
3
0
11
3
0
i/o
frequency to achieve appropriate LIN or
R/(W)
LBT2
LDIV10
LDIV2
R/W
2
0
10
2
0
R/(W)
LBT1
LDIV1
LDIV9
R/W
1
0
1
9
0
R/(W)
LDIV0
LDIV8
LBT0
R/W
0
0
0
8
0
8209D–AVR–11/10
LINBRRL
LINBRRH
LINBTR

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