ATmega16M1 Automotive Atmel Corporation, ATmega16M1 Automotive Datasheet - Page 215

• Manufacturer Part Number: ATmega16M1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega16M1 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.6.2
17.5.6.3
17.5.7
7647G–AVR–09/11
Data Length
Re-synchronization in LIN Mode
Handling LBT[5..0]
When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization
begins when the BREAK is detected. If the BREAK size is not in the range (11 bits min., 28
bits max. — 13 bits nominal), the BREAK is refused. The re-synchronization is done by adjust-
ing LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED
IDENTIFIER is sampled using the new value of LBT[5..0]. The re-synchronization imple-
mented in the controller tolerates a clock deviation of ±20% and adjusts the baud rate in a
±2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be
reset to 32 for the next header.
The LINBTR register can be used to re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
LDISR bit of LINBTR register is used to:
Note that the LENA bit of LINCR register is important for this handling (see
page
Figure 17-8. Handling LBT[5..0]
Section 17.4.6 “LIN Commands” on page 209
set the LRXDL[3..0] or LTXDL[3..0] fields of LINDLR register before receiving or transmitting a
response.
In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number
of bytes already successfully sent.
In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number
of bytes already successfully received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
• To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of
• Disable the re-synchronization in LIN Slave Mode for test purposes.
UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation.
215).
=1
Write in LINBTR register
(LINCR bit 4)
LENA ?
Enable re-synch. in LIN mode
LBT[5..0] forced to 0x20
LDISR forced to 0
=0
LDISR
to write
Atmel ATmega16/32/64/M1/C1
=0
describes how to set or how are automatically
=1
Disable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
LDISR forced to 1
(LBT[5..0]
min
=8)
Figure 17-8 on
215