AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 253

• Manufacturer Part Number: AT90PWM3B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM3B

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 1
• Pwm Channels: 12
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4317J–AVR–08/10
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion
is started. In case the amplifier output is modified during the sample phase of the ADC, the on-
going conversion is aborted and restarted as soon as the output of the amplifier is stable. This
ensure a fast response time. The only precaution to take is to be sure that the trig signal (PSC)
frequency is lower than ADCclk/4.
Figure 21-16. Amplifier synchronization timing diagram for AT90PWM2B/3B
Figure 21-17. Amplifier synchronization timing diagram for AT90PWM2B/3B
Block
ADC
PSC
(Sync Clock)
Si g nal to be
PS Cn_ASY
AMPLI_clk
measu red
CK ADC
Activity
ADSC
ADC
With change on analog input signal
ADSC is set when the amplifier output is changing due to the amplifier clock
switch.
Sampling
ADC
Conv
ADC
ADC Result
Delta V
Ready
AT90PWM2/3/2B/3B
4th stable sample
Sampling
ADC
Valid sample
Conv
ADC
ADC Result
Ready
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