AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 252
AT90PWM3B
Manufacturer Part Number
AT90PWM3B
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM3B
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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AT90PWM2B/3B:
252
AT90PWM2/3/2B/3B
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown
Figure 21-15. Amplifier synchronization timing diagram for AT90PWM2/3.
It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-
sion is started at the next amplifier clock event following the last auto trigger event selected
thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running
mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
Only PSC sources can auto trigger the amplified conversion. In this case, the core must have a
clock synchronous with the PSC. If the PSC uses the PLL clock, the core must use the PLL/4
clock source.
On PWM2B/3B, the amplifier has been improved in order to speed-up the conversion time.The
proposed improvement takes advantage of the amplifier characteristics to ensure a conversion
in less time.
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown
Amplifier
Block
Block
ADC
PSC
Amplifier Sample
Amplifier Hold
(Sync Clock)
Signal to be
PSCn_ASY
AMPLI_clk
measured
ADASCR
CK ADC
Enable
ADSC
Value
Figure 21-15
Figure
for AT90PWM2B/3B.
Delta V
for AT90PWM2/3.
4th stable sample
Sampling
ADC Result Ready
ADC
Valid sample
4317J–AVR–08/10
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