AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 186

• Manufacturer Part Number: AT90PWM3B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM3B

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 1
• Pwm Channels: 12
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.3.2
18.3.3
186
AT90PWM2/3/2B/3B
Double Speed Operation (U2X)
External Clock
Table 18-1
ing the UBRR value for each mode of operation using an internally generated clock source.
Table 18-1.
Note:
Some examples of UBRR values for some system clock frequencies are found in
(see
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
Operating Mode
Asynchronous Normal mode
(U2X = 0)
Asynchronous Double Speed
mode (U2X = 1)
Synchronous Master mode
BAUD Baud rate (in bits per second, bps).
f
UBRR Contents of the UBRRH and UBRRL Registers, (0-4095).
clk
page
io
1. The baud rate is defined to be the transfer rate in bit per second (bps)
System I/O Clock frequency.
207).
contains equations for calculating the baud rate (in bits per second) and for calculat-
Equations for Calculating Baud Rate Register Setting
Figure 18-2
for details.
Equation for Calculating Baud
BAUD
BAUD
BAUD
=
=
=
----------------------------------------- -
16 UBRRn
Rate
-------------------------------------- -
8 UBRRn
-------------------------------------- -
2 UBRRn
f
XCKn
(
(
(
(1)
f
f
f
CLKio
CLKio
CLKio
<
f
--------------- -
CLKio
4
+
+
+
1
1
1
)
)
)
Equation for Calculating UBRR
UBRRn
UBRRn
UBRRn
=
Value
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
CLKio
CLKio
CLKio
4317J–AVR–08/10
Table 18-9
–
–
–