AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 43

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

6. System Clock
Figure 6-1.
Figure 6-2.
3714A–MICRO–7/11
XTAL1A
XTAL2A
XTAL1A
XTAL2A
XTAL1B
XTAL2B
INTERNAL
INTERNAL
8.0 MHz
8.0 MHz
OSC
OSC
AT89LP51RD2/ED2 Clock Subsystem Diagram
AT89LP51ID2 Clock Subsystem Diagram
The AT89LP51RD2/ED2 has a single system clock that is generated directly from one of three
selectable clock sources: on-chip crystal oscillator A in high or low power operation, external
clock source on XTAL1A, and the internal 8 MHz RC oscillator. A diagram of the clock subsys-
tem is shown in
shown in
clock, the AT89LP51ID2 device adds a second system clock source that is selectable from on-
chip low frequency crystal oscillator B in, external clock source on XTAL1B, and the internal 8
MHz RC oscillator. A diagram of this clock subsystem is shown in
selected by the Clock Source B User Fuses as shown in
also affects the start-up time after a POR, BOD or Power-down event (See
or
T h e A T 8 9 L P 5 1 R D 2 / E D 2 / I D 2 i n c l u d e s a X 1 / X 2 f e a t u r e f o r c o m p a t i b i l i t y w i t h
AT89C51RD2/ED2/ID2. This feature determines if the oscillator source is divided by two or not
to generate the system clock. The 8-bit system clock divider may be used to prescale the system
clock to reduce the operating frequency. In addition a 4-bit prescaler is available to change the
clocks of the peripherals.
“Power-down Mode” on page
÷128
0
1
2
3
0
1
2
3
0
1
2
3
Table 6-1
Timer 0 Subclock
Figure
÷2
(See
0
1
6-1. The clock source is selected by the Clock Source A User Fuses as
1
0
“User Configuration Fuses” on page
AT89LP51RD2/ED2/ID2 Preliminary
÷2
Timer 2
(EXTB or XTALB
only via T2 )
58).
DIVIDER
CLOCK
1
0
CKRL
8-BIT
DIVIDER
CLOCK
CKRL
8-BIT
1
0
SYSTEM CLOCK
(CLK
SYS
)
Table
PRESCALER
1
0
SYSTEM CLOCK
4-BIT
(CLK
190). In addition to this system
6-2. The choice of clock source
SYS
Figure
)
PRESCALER
4-BIT
6-2. Clock source B is
Timer 0
Timer 1
Timer 2
PCA
Watchdog
“Reset” on page 53
Timer 0
Timer 1
Timer 2
PCA
Watchdog
43