AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 179

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

22.1
22.1.1
22.1.2
3714A–MICRO–7/11
Description: The forty bits in the M register are shifted one bit to the right. Bit 39 retains its value to preserve the sign of the
Description: BREAK transfers control from normal execution to the On-Chip Debug (OCD) handler if OCD is enabled. The PC
Instruction Set Extensions
Operation: ASR
Operation: BREAK
Encoding:
Encoding:
Function: Shift MAC Accumulator Right Arithmetically
Function: Software Breakpoint (Halt execution)
ASR M
BREAK
Example: The M register holds the value 0C5B1A29384H . The following instruction,
Example: If On-Chip Debugging is allowed, the following instruction,
Cycles: 2
Cycles: 2
Bytes: 2
Bytes: 2
value. No flags are affected.
ASR M
leaves the M register holding the value 0E2D8D149C2H.
(M
(M
is left pointing to the following instruction. If OCD is disabled, BREAK acts as a double NOP. No flags are
affected.
BREAK
will halt instruction execution prior to the immediately following instruction. If debugging is not allowed, the
BREAK is treated as a double NOP.
(PC) ← (PC) + 2
n
39
) ← (M
A5
A5
) ← (M
The following instructions are extensions to the standard 8051 instruction set that provide
enhanced capabilities not found in standard 8051 devices. All extended instructions start with an
A5H escape code. For this reason random A5H reserved codes should not be placed in the
instruction stream even though other devices may have treated these as NOPs.
Other AT89LP devices may not support all of these instructions.
n + 1
39
)
) n = 0 - 38
2. This escaped instruction is an extension to the instruction set.
3. This is the minimum time for MOVX with no wait states. In Compatibility mode an additional 24
defaults to 2, so the clock cycle is twice the oscillator period, or conversely the clock count is
half the number of oscillator periods.
clocks are added for the wait state. In Fast mode, 1 clock is added for each wait state (0–3).
0
0
0
0
0
0
AT89LP51RD2/ED2/ID2 Preliminary
0
0
0
0
0
0
1
0
1
0
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