AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 216

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

216
AT89LP51RD2/ED2/ID2 Preliminary
The Parallel interface is a special mode of the serial interface, i.e. the serial interface is used to
enable the parallel interface. After enabling the interface serially over P1.7/SCK and P1.5/MOSI,
P1.5 is reconfigured as an active-low output enable (OE) for data on Port 0. When OE = 1, com-
mand, address and write data bytes are input on Port 0 and sampled at the rising edge of SCK.
When OE = 0, read data bytes are output on Port 0 and should be sampled on the falling edge of
SCK. The P1.7/SCK and RST pins continue to function in the same manner. With the addition of
VDD and GND, the parallel interface requires a minimum of fourteen connections as shown in
Figure
interface.
Figure 24-18. Parallel Programming Device Connections
The Programming Interface is a means of externally programming the AT89LP51RD2/ED2/ID2
microcontroller. The Interface can be used to program the device both in-system and in a stand-
alone serial programmer. The Interface does not require any clock other than SCK and is not
limited by the system clock frequency. During Programming the system clock source of the tar-
get device can operate normally.
When designing a system where In-System Programming will be used, the following observa-
tions must be considered for correct operation:
• The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a
• The AT89LP51RD2/ED2/ID2 will enter programming mode only when its reset line (RST) is
• The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP
• For standalone programmers, an active-low reset polarity is recommended (POL = 0). RST
maximum frequency of 5 MHz.
active. To simplify this operation, it is recommended that the target reset can be controlled by
the In-System programmer. To avoid problems, the In-System programmer should be able to
keep the entire target system reset for the duration of the programming cycle. The target
system should never attempt to drive the three SPI lines while reset is active.
Fuse is disabled, ISP may only be entered at POR. To enter programming the RST pin must
be driven active prior to the end of Power-On Reset (POR). After POR has completed the
device will remain in ISP mode until RST is brought inactive. Once the initial ISP session has
ended, the power to the target device must be cycled OFF and ON to enter another session.
Note that if this method is required, an active-low reset polarity is recommended.
may then be tied directly to GND to ensure correct entry into Programming mode regardless
of the device settings.
24-18. Note that a connection to P1.6/MISO is not required for using the parallel
Clock
RST
OE
SS
AT89LP51RD2/ED2/ID2
P1.7/SCK
RST
P1.5/MOSI
P1.4/SS
GND
P0.7-0
VDD
POL
8
GND or VDD
Data In/Out
3714A–MICRO–7/11