AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 131

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

18.2
18.3
3714A–MICRO–7/11
Master Operation
Slave Operation
An SPI master device initiates all data transfers on the SPI bus. The AT89LP51RD2/ED2/ID2 is
configured for master operation by setting MSTR = 1 in SPCON. Writing to the SPI data register
(SPDAT) while in master mode loads the transmit buffer. If the SPI shift register is empty, the
byte in the transmit buffer is moved to the shift register; the transmit buffer empty flag, TXE, is
set; and a transmission begins. The transfer may start after an initial delay, while the clock gen-
erator waits for the next full bit slot of the specified baud rate. The master shifts the data out
serially on the MOSI line while providing the serial shift clock on SCK. When the transfer fin-
ishes, the SPIF flag is set to “1” and an interrupt request is generated, if enabled. The data
received from the addressed SPI slave device is also transferred from the shift register to the
receive buffer. Therefore, the SPIF bit flags both the transmit-complete and receive-data-ready
conditions. The received data is accessed by reading SPDAT.
While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by
writing to SPDAT. Writing to SPDAT will clear TXE and load the transmit buffer. The user may
load the buffer while the shift register is busy, i.e. before the current transfer completes. When
the current transfer completes, the queued byte in the transmit buffer is moved to the shift regis-
ter and the next transfer commences. TXE will generate an interrupt if the SPI interrupt is
enabled and if the ENH bit in SPSTA is set. For multi-byte transfers, TXE may be used to
remove any dead time between byte transmissions.
The SPI master can operate in two modes: multi-master mode and single-master mode. By
default, multi-master mode is active when SSIG = 0. In this mode, the SS input is used to dis-
able a master device when another master is accessing the bus. When SS is driven low, the
master device becomes a slave by clearing its MSTR bit and a Mode Fault is generated by set-
ting the MODF bit in SPSTA. MODF will generate an interrupt if enabled. The MSTR bit must be
set in software before the device may become a master again. Single-master mode is enabled
by setting SSIG = 1. In this mode SS is ignored and the master is always active. SS may be
used as a general purpose I/O in this mode.
When the AT89LP51RD2/ED2/ID2 is not configured for master operation, MSTR = 0, it will oper-
ate as an SPI slave. In slave mode, bytes are shifted in through MOSI and out through MISO by
a master device controlling the serial clock on SCK. When a byte has been transferred, the SPIF
flag is set to “1” and an interrupt request is generated, if enabled. The data received from the
addressed master device is also transferred from the shift register to the receive buffer. The
received data is accessed by reading SPDAT. A slave device cannot initiate transfers. Data to
be transferred to the master device must be preloaded by writing to SPDAT. Writes to SPDAT
are double-buffered. The transmit buffer is loaded first and if the shift register is empty, the con-
tents of the buffer will be transferred to the shift register.
While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by
writing to SPDAT. Writing to SPDAT will clear TXE and load the transmit buffer. The user may
load the buffer while the shift register is busy, i.e. before the current transfer completes. When
the current transfer completes, the queued byte in the transmit buffer is moved to the shift regis-
ter and waits for the master to initiate another transfer. TXE will generate an interrupt if the SPI
interrupt is enabled and if the ENH bit in SPSTA is set.
The SPI slave can operate in two modes: 4-wire mode and 3-wire mode. By default, 4-wire
mode is active when SSIG = 0. In this mode, the SS input is used to enable/disable the slave
device when addressed by a master. When SS is driven low, the slave device is enabled and will
AT89LP51RD2/ED2/ID2 Preliminary
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